Modelsim Working + Simulating + dumping - Some bugs

rtl/shared_memory/VX_priority_encoder_sm.v

@@ -7,8 +7,8 @@ module VX_priority_encoder_sm
 	)
 	(
 	//INPUTS
-	input wire				clk,
-	//input wire				reset,
+	input wire			        	clk,
+	input wire				        reset,
 	input wire[`NT_M1:0]			in_valid,
 	input wire[`NT_M1:0][31:0] 		in_address,
 	input wire[`NT_M1:0][31:0] 		in_data,
@@ -25,6 +25,8 @@ module VX_priority_encoder_sm
 );
 
 	reg[`NT_M1:0] left_requests;
+	reg[`NT_M1:0] serviced;
+
 
 	wire[`NT_M1:0] use_valid;
 
@@ -71,7 +73,6 @@ module VX_priority_encoder_sm
 		assign out_data[curr_bank_o]    = internal_out_valid[curr_bank_o] ? in_data[internal_req_num[curr_bank_o]] : 0;
 	end
 
-	reg[`NT_M1:0] serviced;
 	integer curr_b;
 	always @(*) begin
 		serviced = 0;
@@ -91,9 +92,14 @@ module VX_priority_encoder_sm
 
 	// wire[`NT_M1:0] new_left_requests = left_requests & ~(serviced_qual);
 
-	always @(posedge clk) begin
-		if (!stall)    left_requests <= 0;
-		else           left_requests <= new_left_requests;
+	always @(posedge clk, posedge reset) begin
+		if (reset) begin
+			left_requests <= 0;
+			serviced       = 0;
+		end else begin
+			if (!stall)    left_requests <= 0;
+			else           left_requests <= new_left_requests;
+		end
 	end
 
 endmodule

rtl/shared_memory/VX_shared_memory.v

@@ -8,6 +8,7 @@ module VX_shared_memory
 	(
 	//INPUTS
 	input wire clk,
+	input wire reset,
 	input wire[`NT_M1:0] in_valid,
 	input wire[`NT_M1:0][31:0] in_address,
 	input wire[`NT_M1:0][31:0] in_data,
@@ -52,7 +53,7 @@ genvar f;
 
 VX_priority_encoder_sm #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_encoder_sm(
 	.clk(clk),
-	//.reset(reset),
+	.reset(reset),
 	.in_valid(orig_in_valid),
 	.in_address(in_address),
 	.in_data(in_data),
@@ -71,12 +72,13 @@ integer i;
 generate
 for(j=0; j<= NB; j=j+1) begin
 	VX_shared_memory_block vx_shared_memory_block(
-		.clk(clk),
-		.addr(block_addr[j]),
-		.wdata(block_wdata[j]),
-		.we(block_we[j]),
+		.clk      (clk),
+		.reset    (reset),
+		.addr     (block_addr[j]),
+		.wdata    (block_wdata[j]),
+		.we       (block_we[j]),
 		.shm_write(shm_write),
-		.data_out(block_rdata[j])
+		.data_out (block_rdata[j])
 	);
 end	
 

rtl/shared_memory/VX_shared_memory_block.v

@@ -1,9 +1,10 @@
 module VX_shared_memory_block (
-	input clk,    // Clock
-	input wire[6:0]       addr,
-	input wire[3:0][31:0] wdata,
-	input wire[1:0] we,
-	input wire shm_write,
+	input wire             clk,    // Clock
+	input wire             reset,
+	input wire[6:0]        addr,
+	input wire[3:0][31:0]  wdata,
+	input wire[1:0]        we,
+	input wire             shm_write,
 
 	output wire[3:0][31:0] data_out
 	
@@ -12,12 +13,17 @@ module VX_shared_memory_block (
 
 	`ifndef SYN
 
-		logic [3:0][31:0] shared_memory[127:0];
+		reg[3:0][31:0] shared_memory[127:0];
 
 		//wire need_to_write = (|we);
-
-		always @(posedge clk) begin
-			if(shm_write) begin
+		integer curr_ind;
+		always @(posedge clk, posedge reset) begin
+			if (reset) begin
+				for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1)
+				begin
+					shared_memory[curr_ind] = 0;
+				end
+			end else if(shm_write) begin
 				if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0]; 
 				if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0]; 
 				if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];