Modelsim Working + Simulating + dumping - Some bugs

2019-10-27 03:36:02 -04:00
parent 372c81d90c
commit 715982cca7
24 changed files with 374 additions and 142 deletions
--- a/rtl/VX_gpr_wrapper.v
+++ b/rtl/VX_gpr_wrapper.v
@@ -2,6 +2,7 @@

 module VX_gpr_wrapper (
 	input wire                  clk,
+	input wire                  reset,
 	VX_gpr_read_inter           VX_gpr_read,
 	VX_wb_inter                 VX_writeback_inter,	
 	VX_gpr_jal_inter            VX_gpr_jal,
@@ -30,6 +31,7 @@ module VX_gpr_wrapper (
 			wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
 			VX_gpr vx_gpr(
 				.clk                (clk),
+				.reset              (reset),
 				.valid_write_request(valid_write_request),
 				.VX_gpr_read        (VX_gpr_read),
 				.VX_writeback_inter (VX_writeback_inter),