From 70bd6730313c9f7807607548de9fba827916687c Mon Sep 17 00:00:00 2001
From: felsabbagh3 <felsabbagh3@gatech.edu>
Date: Sat, 4 Apr 2020 10:13:26 -0700
Subject: [PATCH] Resseting GPR

---
 rtl/byte_enabled_simple_dual_port_ram.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtl/byte_enabled_simple_dual_port_ram.v b/rtl/byte_enabled_simple_dual_port_ram.v
index 73b923f4..b4dcf5fc 100644
--- a/rtl/byte_enabled_simple_dual_port_ram.v
+++ b/rtl/byte_enabled_simple_dual_port_ram.v
@@ -25,9 +25,9 @@ module byte_enabled_simple_dual_port_ram
 	always @(posedge clk, posedge reset) begin
 		// TODO Clearing ram not currently supported on FPGA.
 		if (reset) begin
-`ifdef ASIC
+// `ifdef ASIC
 			for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] <= 0;
-`endif
+// `endif
 		end 
 		else if(we) begin
 			integer thread_ind;