moving MUL unit into ALU unit

2021-02-23 13:49:02 -08:00
parent 1792571e1b
commit 700f9eea19
30 changed files with 112978 additions and 9680 deletions
--- a/hw/rtl/cache/VX_shared_mem.v
+++ b/hw/rtl/cache/VX_shared_mem.v
@@ -164,7 +164,7 @@ module VX_shared_mem #(
        ) data (
            .clk    (clk),
            .addr   (per_bank_core_req_addr[i]),          
-            .wren   (per_bank_core_req_valid[i] && per_bank_core_req_rw[i] && crsq_in_ready),  
+            .wren   (per_bank_core_req_valid[i] && per_bank_core_req_rw[i]),  
            .byteen (per_bank_core_req_byteen[i]),
            .rden   (1'b1),
            .din    (per_bank_core_req_data[i]),