moving MUL unit into ALU unit

hw/rtl/cache/VX_bank.v

@@ -301,7 +301,7 @@ module VX_bank #(
         // read/Fill
         .lookup     (valid_st0 && !is_fill_st0),
         .addr       (addr_st0),        
-        .fill       (valid_st0 && is_fill_st0),
+        .fill       (valid_st0 && is_fill_st0 && !crsq_in_stall),
         .is_flush   (is_flush_st0),
         .tag_match  (tag_match_st0)
     );

hw/rtl/cache/VX_cache.v

@@ -20,7 +20,7 @@ module VX_cache #(
     // Core Request Queue Size
     parameter CREQ_SIZE                     = 4, 
     // Miss Reserv Queue Knob
-    parameter MSHR_SIZE                     = 16, 
+    parameter MSHR_SIZE                     = 8, 
     // DRAM Response Queue Size
     parameter DRSQ_SIZE                     = 4,
     // DRAM Request Queue Size

hw/rtl/cache/VX_shared_mem.v

@@ -164,7 +164,7 @@ module VX_shared_mem #(
         ) data (
             .clk    (clk),
             .addr   (per_bank_core_req_addr[i]),          
-            .wren   (per_bank_core_req_valid[i] && per_bank_core_req_rw[i] && crsq_in_ready),  
+            .wren   (per_bank_core_req_valid[i] && per_bank_core_req_rw[i]),  
             .byteen (per_bank_core_req_byteen[i]),
             .rden   (1'b1),
             .din    (per_bank_core_req_data[i]),