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Operand\001 -4 1 0 50 -1 16 8 0.0000 4 120 735 3960 945 log2(#pregs)\001 -4 1 0 50 -1 16 8 0.0000 4 120 735 5445 945 log2(#pregs)\001 -4 1 0 50 -1 18 8 0.0000 4 120 1155 5400 1305 Pred. Reg. Operand\001 -4 1 0 50 -1 18 8 0.0000 4 120 810 6840 1305 Imm. Operand\001 -4 1 0 50 -1 16 8 0.0000 4 120 825 6840 945 Remaining bits\001 -4 1 0 50 -1 18 8 0.0000 4 135 1110 3600 405 One (aligned) word\001 diff --git a/doc/harp_iset.tex b/doc/harp_iset.tex deleted file mode 100644 index 23a8f457..00000000 --- a/doc/harp_iset.tex +++ /dev/null @@ -1,442 +0,0 @@ -\documentclass[10pt,letterpaper]{article} - -\usepackage[margin=1in]{geometry} -\usepackage{graphicx} -\title{HARP Instruction Set Manual} -\author{Chad D. Kersey} - -\begin{document} -\maketitle -\section*{Disclaimer} -This document, like the work it documents, is very much a work in progress. -Send any corrections, updates, suggestions, or complaints (preferably in patch form, this file is under \texttt{harptool/doc} in the HarpTool repo) to \texttt{cdkersey@gatech.edu}. - -\section*{Introduction} -HARP is two things, a multi-year Heterogeneous Architecture Research Project, and an implementation of a specific Heterogeneous Architecture Research Prototype. -It is for the latter that the HARP instruction set architectures have been created. -This is a space of SIMT(GPU) oriented RISC-like instruction sets with the following properties: - -\begin{itemize} - \item{Full predication} - \item{Assembly language level compatibility} - \item{SIM[DT] parallelism} - \item{Little endianness} - \item{8-bit byte size} - \item{Customizability} -\end{itemize} - -The customizability of the HARP ISAs is illustrated by facts missing from this list of features. -The data path width, instruction encodings, number of registers (general purpose and predicate) are all left up to the implementation. -Harptool; the HARP assembler, linker, emulator, and disassembler, is passed information about the ISA through an architecture identifier string, or \texttt{ArchID}. -An \texttt{ArchID} uniquely identifies a HARP ISA. - -\section{Architecture Identifier String (\texttt{ArchID})} -The best way to understand the multifaceted parameterizablity of the HARP ISAs is to study the architecture identifier strings used to uniquely identify a single HARP instruction set architecture. -We'll start by breaking down Harptool's default \texttt{ArchID}: \texttt{8w32/32/8/8}: - -\begin{center} -\begin{tabular}{rl} -\textbf{Field}&\textbf{Meaning}\\ -\hline -\texttt{8} &8-byte (64-bit) registers and addresses\\ -\texttt{w} &Word-based (64-bit) fixed-width instruction encoding\\ -\texttt{32}&32 general-purpose registers per lane\\ -\texttt{32}&32 predicate registers per lane\\ -\texttt{8} &8 SIMD lanes\\ -\texttt{8} &8 warps (thread groups)\\ -\end{tabular} -\end{center} - -All ArchIDs have a similar format, although the final two fields can be omitted, as object files are still fully compatible even if the dimensions of the core change. - -\section{HarpTool} -The assembler/linker/emulator/disassembler program for HARP is called HarpTool. -It is a multiple-function executable, its function selected with the first command line argument. -When run with no command line arugments the HarpTool executable prints a help message explaining the available command line arguments. - -All of the HARP utilities can take an archID as a command line parameter. -If none is provided, a default will be assumed. - -\subsection{Assembler} -The assembler converts assembly files to HOF, the Harp Object Format. - -\subsection{Linker} -The linker combines HOF files and produces raw RAM images for use by the emulator. -An intended future use is the conversion of multiple HOF files to statically-linked HOF executables. - -%\subsection{Emulator} -%The emulator emulates a HARP system. -%It can be provided with a - -\subsection{Disassembler} -The disassembler is used to convert HOF files to equivalent assembly files. -One of its intended uses is the conversion of HOF object files between different HARP ISAs, say from 8w32/32 to 8b32/32. - -\subsection{Test Programs} -In the \texttt{harptool/test} directory there is a set of test programs. -The makefile in this directory assembles, links, and emulates them, placing the output in plain text files. - -\subsubsection{\texttt{hello.s}} -The simplest example prints a message and exits. - -\subsubsection{\texttt{2thread.s}} -\texttt{2thread} performs a vector addition across two threads. - -\subsubsection{\texttt{sieve.s}} -\texttt{sieve} performs the Sieve of Eratosthenes in a single thread and prints the results, including the count of total prime numbers found. - -\section{Instruction Encoding} -There are two currently-supported types of instruction encoding, but they all share a similar basic structure. -The opcodes and types of fields required by each instruction are identical, differentiated only by the number of bits available for each type of field and the way predication is specified. - -\subsection{Argument Classes} -Instructions can be broadly categorized by the types of arguments they require. -The bit fields in the instruction encodings depend heavily on this quality. - -\begin{center} -\begin{tabular}{c|c|l} -\textbf{Argument Class}&\textbf{Description}&\textbf{Example}\\ -\hline -\texttt{AC\_NONE} &No arguments &\texttt{di;} \\ -\texttt{AC\_2REG} &2 GPRs, 1 in, 1 out &\texttt{neg \%r1, \%r2;} \\ -\texttt{AC\_2IMM} &1 immediate in, 1 GPR out&\texttt{ldi \%r1, \#0xff;}\\ -\texttt{AC\_3REG} &3 GPRs, 2 in, 1 out &\texttt{add \%r1, \%r2, \%r2;}\\ -\texttt{AC\_3PREG} &3 pred. regs, 2 in, 1 out&\texttt{andp @p0, @p0, @p1;}\\ -\texttt{AC\_3IMM} &GPR in, imm. in, GPR out &\texttt{andi \%r1, \%r3, \#3;}\\ -\texttt{AC\_3REGSRC} &3 GPRs in &\texttt{tlbadd \%r0, \%r1, \%r2;}\\ -\texttt{AC\_1IMM} &1 imm in &\texttt{jmpi label;} \\ -\texttt{AC\_1REG} &1 reg in &\texttt{jmpr \%r2} \\ -\texttt{AC\_3IMMSRC} &2 GPRs in, 1 imm. in &\texttt{st \%r1, \%r2, \#10;}\\ -\texttt{AC\_PREG\_REG}&GPR in, pred. reg. out &\texttt{iszero @p0, \%r3;} \\ -\texttt{AC\_2PREG} &2 pred. regs, 1 in, 1 out&\texttt{notp @p0, @p0;} \\ -\end{tabular} -\end{center} - -\subsection{Opcode/Instruction Class Table} -\begin{verbatim} - 00 "nop" NONE 01 "di" NONE 02 "ei" NONE - 03 "tlbadd" 3REGSRC 04 "tlbflush" NONE 05 "neg" 2REG - 06 "not" 2REG 07 "and" 3REG 08 "or" 3REG - 09 "xor" 3REG 0a "add" 3REG 0b "sub" 3REG - 0c "mul" 3REG 0d "div" 3REG 0e "mod" 3REG - 0f "shl" 3REG 10 "shr" 3REG 11 "andi" 3IMM - 12 "ori" 3IMM 13 "xori" 3IMM 14 "addi" 3IMM - 15 "subi" 3IMM 16 "muli" 3IMM 17 "divi" 3IMM - 18 "modi" 3IMM 19 "shli" 3IMM 1a "shri" 3IMM - 1b "jali" 2IMM 1c "jalr" 2REG 1d "jmpi" 1IMM - 1e "jmpr" 1REG 1f "clone" 1REG 20 "jalis" 3IMM - 21 "jalrs" 3REG 22 "jmprt" 1REG 23 "ld" 3IMM - 24 "st" 3IMMSRC 25 "ldi" 2IMM 26 "rtop" PREG_REG - 27 "andp" 3PREG 28 "orp" 3PREG 29 "xorp" 3PREG - 2a "notp" 2PREG 2b "isneg" PREG_REG 2c "iszero" PREG_REG - 2d "halt" NONE 2e "trap" NONE 2f "jmpru" 1REG - 30 "skep" 1REG 31 "reti" NONE 32 "tlbrm" 1REG - 33 "itof" 2REG 34 "ftoi" 2REG 35 "fadd" 3REG - 36 "fsub" 3REG 37 "fmul" 3REG 38 "fdiv" 3REG - 39 "fneg" 2REG 3a "wspawn" 3REG 3b "split" NONE - 3c "join" NONE 3d "bar" -\end{verbatim} - -\subsection{Word Encoding} - -Word-based instruction encodings all share the initial fields: -\begin{itemize} - \item The most-significant bit is 1 if the instruction is predicated and 0 otherwise. - \item The next $log_2(\mathrm{\#pred\_regs})$ specify the predicate register. - \item The next 6 bits are used for the opcode. -\end{itemize} - -After this, the operands of the instruction are ordered corresponding to their ordering in the assembly language, sized according to the following rules: -\begin{itemize} - \item Register operands are $log_2(\mathrm{\#GPRs})$ bits long, or just enough bits to uniquely identify a register. - \item Predicate register operands are $log_2(\mathrm{\#pred\_regs})$ bits long, or just enough bits to uniquely identify a predicate register. - \item Immediate fields are always the last field and occupy the remaining bits of the instruction. All immediate fields are sign extended to the length of a machine word. -\end{itemize} - -\begin{center} -\includegraphics{fig/word_enc} -\end{center} - -\subsection{Byte Encoding} -In the byte encoding, each field of the instruction (predicate, opcode, operands) occupies a byte, with the exception of immediates, which occupy an unaligned word. -All instructions have a predicate and opcode byte. -The predicate byte is all ones if the instruction is not predicated; oterwise the predicate byte contains the predicate register number used to predicate the instruction. -Just like the word-based instruction encoding, registers appear in the same order as the assembly language, destination-first. - -\begin{center} -\includegraphics{fig/byte_enc} -\end{center} - -\section{Assembly Language} -The assembly language is fairly easy to pick up from the HarpTools examples. It is RISC-like, and written destination register first (in this it differs from Unix assembly syntax). -Registers names are prefixed with the percent sign (\%) and predicate register names with the at symbol (@). -Predicated instructions are prefixed with the predicate register name and a question mark: -\begin{verbatim} - @p0 ? addi %r7, %r1, #1 -\end{verbatim} -A small set of directives is provided to express non-instruction data: - -\begin{center} -\begin{tabular}{cl} -\textbf{Directive}&\textbf{Use}\\ -\hline -\texttt{.align 256} &Align next symbol to a multiple of 256 bytes.\\ -\texttt{.word 0x1234} &Insert a word with the value \texttt{0x1234}.\\ -\texttt{.byte 0xff} &Insert a byte with the value \texttt{0xff}.\\ -\texttt{.def SYM 123} &Replace SYM with 123 in immediate operands.\\ -\texttt{.entry} &Make the next label the HOF executable entry point.\\ -\texttt{.global} &Give the next label global (external) linkage.\\ -\texttt{.perm rw} &Set HOF permissions of the next label to read/write.\\ -\texttt{.string "Str"} &Create a null terminated string.\\ -\end{tabular} -\end{center} - -\section{Instruction Set} -\subsection{Trivial Instruction} -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{nop}&No operation.\\ -\end{tabular} -\end{center} - -\subsection{Privileged Instructions} -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{ei} &Enable interrupts.\\ -\texttt{di} &Disable interrupts.\\ -\texttt{skep} \%addr&Set kernel entry point.\\ -\texttt{tlbadd} \%virt, \%phys, \%flags&Add an entry to the TLB.\\ -\texttt{tlbrm} \%virt&Remove entry corresponding to virt. address from TLB.\\ -\texttt{tlbflush}&Remove all but default entry from TLB.\\ -\texttt{jmpru} \%addr&Jump indirect and switch to user mode.\\ -\texttt{reti}&Return from interrupt.\\ -\texttt{halt}&Halt CPU until next interrupt.\\ -\end{tabular} -\end{center} - -The flags register used by \texttt{tlbadd} stores, in its least-significant four bits, in order from most to least significant: -\begin{center} -\begin{tabular}{cl}\ -\textbf{Bit}&\textbf{Meaning}\\ -\hline - \texttt{kx}&Kernel can execute.\\ - \texttt{kw}&Kernel can write.\\ - \texttt{kr}&Kernel can read.\\ - \texttt{ux}&User can execute.\\ - \texttt{uw}&User can write.\\ - \texttt{ur}&User can read.\\ -\end{tabular} -\end{center} - -\subsection{Memory Loads/Stores} -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{st} \%val, \%base, \textsc{\#Offset}&Store.\\ -\texttt{ld} \%dest, \%base, \textsc{\#Offset}&Load.\\ -\end{tabular} -\end{center} - -\subsection{Predicate Manipulation} - -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{andp} @dest, @src1, @src2&Logical and.\\ -\texttt{orp} @dest, @src1, @src2&Logical or.\\ -\texttt{xorp} @dest, @src1, @src2&Exclusive or.\\ -\texttt{notp} @dest, @src&Complement.\\ -\end{tabular} -\end{center} - -\subsection{Value Tests} - -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{rtop} @dest, \%src&Set @dest if \%src is nonzero.\\ -\texttt{isneg} @dest, \%src&Set @dest if \%src is negative.\\ -\texttt{iszero} @dest, \%src&Set @dest if \%src is zero.\\ -\end{tabular} -\end{center} - -\subsection{Immediate Integer Arithmetic/Logic} - -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{ldi} \%dest, \textsc{\#Imm}&Load immediate.\\ -\texttt{addi} \%dest, \%src1, \textsc{\#Imm}&Add immediate.\\ -\texttt{subi} \%dest, \%src1, \textsc{\#Imm}&Subtract immediate.\\ -\texttt{muli} \%dest, \%src1, \textsc{\#Imm}&Multiply immediate.\\ -\texttt{divi} \%dest, \%src1, \textsc{\#Imm}&Divide immediate.\\ -\texttt{modi} \%dest, \%src1, \textsc{\#Imm}&Modulus immediate.\\ -\texttt{shli} \%dest, \%src1, \textsc{\#Imm}&Shift left immediate.\\ -\texttt{shri} \%dest, \%src1, \textsc{\#Imm}&Shift right immediate.\\ -\texttt{andi} \%dest, \%src1, \textsc{\#Imm}&And immediate.\\ -\texttt{ori} \%dest, \%src1, \textsc{\#Imm}&Or immediate.\\ -\texttt{xori} \%dest, \%src1, \textsc{\#Imm}&Xor immediate.\\ -\end{tabular} -\end{center} - -\subsection{Register Integer Arithmetic/Logic} -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{add} \%dest, \%src1, \%src2&Add.\\ -\texttt{sub} \%dest, \%src1, \%src2&Subtract.\\ -\texttt{mul} \%dest, \%src1, \%src2&Multiply.\\ -\texttt{div} \%dest, \%src1, \%src2&Divide.\\ -\texttt{mod} \%dest, \%src1, \%src2&Modulus.\\ -\texttt{shl} \%dest, \%src1, \%src2&Shift left.\\ -\texttt{shr} \%dest, \%src1, \%src2&Shift right.\\ -\texttt{and} \%dest, \%src1, \%src2&And.\\ -\texttt{or} \%dest, \%src1, \%src2&Or.\\ -\texttt{xor} \%dest, \%src1, \%src2&Xor.\\ -\texttt{neg} \%dest, \%src1&Two's complement.\\ -\texttt{not} \%dest, \%src1&Bitwise complement.\\ -\end{tabular} -\end{center} - -\subsection{Floating Point Arithmetic} -These operations operate on real numbers in an implementation-determined -format, which can be fixed point or floating point. - -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{itof} \%dest, \%src&Signed integer to floating point.\\ -\texttt{ftoi} \%dest, \%src&Floating point to signed integer.\\ -\texttt{fneg} \%dest, \%src&Negate (complement sign bit).\\ -\texttt{fadd} \%dest, \%src1, \%src2&Floating point add.\\ -\texttt{fsub} \%dest, \%src1, \%src2&Floating point subtract.\\ -\texttt{fmul} \%dest, \%src1, \%src2&Floating point multiply.\\ -\texttt{fdiv} \%dest, \%src1, \%src2&Floating point divide.\\ -\end{tabular} -\end{center} - -\subsection{Control Flow} - -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{jmpi} \textsc{\#RelDest}&Jump to immediate (PC-relative).\\ -\texttt{jmpr} \%addr&Jump indirect.\\ -\texttt{jali} \%link, \textsc{\#RelDest}&Jump and link immediate.\\ -\texttt{jalr} \%link, \%reg&Jump and link indirect.\\ -\end{tabular} -\end{center} - -\subsection{SIMD Control} - -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{clone} \%lane&Clone register state into specified lane.\\ -\texttt{jalis} \%link, \%n, \textsc{\#RelDest}&Jump and link immediate, spawning N active lanes.\\ -\texttt{jalrs} \%link, \%n, \%dest&Jump and link indirect, spawning N active lanes.\\ -\texttt{jmprt} \%addr&Jump indirect, terminating execution on all but a single lane.\\ -\texttt{split}&Control flow diverge.\\ -\texttt{join}&Control flow reconverge.\\ -\end{tabular} -\end{center} - -\subsection{Warp Control} -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{wspawn} \%dest, \%pc, \%src&Create new warp, copying \%src in current warp to to \%dest in new warp.\\ -\texttt{bar} \%id, \%n&Barrier of \%n warps. Identified by \%id.\\ -\end{tabular} -\end{center} - -\subsection{User/Kernel Interteraction} - -\begin{center} -\begin{tabular}{cl} -\textbf{Instruction}&\textbf{Description}\\ -\hline -\texttt{trap}&User-generated interrupt.\\ -\end{tabular} -\end{center} - -\section{Interrupts} -The HARP interrupt mechanism is simple. -For SIMD lane 0, there is a shadow register file, program counter, and active lane count. -When an interrupt occurs, the state of lane zero is saved into these shadow registers, and execution resumes at the kernel entry point. -The type of interrupt is specified by the value placed in register 0 at this time, according to the following table: - -\begin{center} -\begin{tabular}{cl} -\textbf{Number}&\textbf{Description}\\ -\hline -0 &Trap (user-generated interrupt)\\ -1 &Page fault due to absence from TLB\\ -2 &Page fault due to permission violation\\ -3 &Invalid/unsupported instruction\\ -4 &Divergent branch\\ -5 &Numerical domain (divide by zero)\\ -6-7&(reserved for future exceptions)\\ -8 &Console input\\ -\end{tabular} -\end{center} - -The first eight interrupt numbers are reserved for internal CPU-generated exceptions, and all of the remaining numbers are free for use by hardware. - -\section{Application Binary Interface} -The ABI assumes a set of at least four general purpose registers. -The frame pointer is optional and can be stored on the stack itself if necessary. -The stack pointer and link register, in this order, are always the two highest-numbered registers. -If 8 or more registers are available, the frame pointer may be the register one less than the register number of the stack pointer. - -\begin{itemize} - \item The lower-numbered half of the registers are caller-saved (temporary). - \item The upper-numbered half are therefore callee-saved. - \item The callee is responsible for adjusting the stack and frame pointers, if such adjustment is required. - \item The stack grows toward smaller addresses (subtract to push, add to pop). - \item Pointer function arguments and numerical arguments that can fit in a single register are passed through temporary registers, starting with register \texttt{\%r0}. If more registers are required than there are temporary registers available, stack space at addresses less than the stack pointer is used. - \item Record (struct) return values and numerical return values larger than the word size are always passed on the stack. The caller is responsible for allocating the necessary space. The stack pointer at the time of call is a pointer to the returned structure. All other return values are returned in \texttt{\%r0}. -\end{itemize} - -\section{SIMD Operation} -The HARP ISAs are inherently SIMD. -In addition to designs with a single set of functional units and architectural registers, designs are allowed that replicate these while retaining a single front-end and memory system. -This allows for multiple threads executing the same stream of instructions to simultaneously occupy multiple ``lanes'' of the processor. -When a predicated control flow instruction occurs without unanimous agreement among predicate registers, a divergent branch has occurred. -The current response to this is to trap to the operating system (interrupt number 4). - -%\begin{center} -%\includegraphics{fig/simd_core} -%\end{center} - -\subsection{Instructions for SIMD Operation} -The \texttt{clone}, \texttt{jalis}, \texttt{jalrs}, and \texttt{jmprt} instructions form the basis of SIMD context control in the HARP instruction set. -Context is created using \texttt{clone}, the waiting threads are spawned using \texttt{jalrs} or \texttt{jalis}, ``jump-and-link immediate/register and spawn'', and finally the parallel section returns using \texttt{jmprt}, ``jump register and terminate'', best thought of as ``return and terminate.'' - -There are times when a control flow operation will need to be predicated, going one direction on some lanes and the other direction on other lanes. -For this, the HARP instruction set provides the \texttt{split} and \texttt{join} instructions. -When a predicated \texttt{split} is first encountered, only the lanes for which the \texttt{split}'s predicate are true are allowed to continue. -The other lanes are masked out until the corresponding \texttt{join} is encountered. -The first time \texttt{join} is reached, control flow returns to the instruction following the corresponding \texttt{split} with the set of masked-out lanes complemented. -The second time the same \texttt{join} is reached, control flow falls through and the original lane mask is restored. -A hardware stack is maintained to keep track of nested \texttt{split}s. - -\section{Default I/O Devices} -The emulator currently only supports a single I/O device, simple console I/O. -Writing to the address \texttt{0x800...0} (an address with its MSB set and all other bits cleared) causes text to be written to the display. -Input on this console interface causes an interrupt (number 8). - -\end{document} diff --git a/src/.DS_Store b/emulator/.DS_Store similarity index 100% rename from src/.DS_Store rename to emulator/.DS_Store diff --git a/src/BUGS b/emulator/BUGS similarity index 100% rename from src/BUGS rename to emulator/BUGS diff --git a/src/LICENSE b/emulator/LICENSE similarity index 100% rename from src/LICENSE rename to emulator/LICENSE diff --git a/src/Makefile b/emulator/Makefile similarity index 100% rename from src/Makefile rename to emulator/Makefile diff --git a/src/WISHLIST b/emulator/WISHLIST similarity index 100% rename from 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similarity index 100% rename from src/riscv_tests/I-LUI-01.elf.hex rename to emulator/riscv_tests/I-LUI-01.elf.hex diff --git a/src/riscv_tests/I-LW-01.elf.hex b/emulator/riscv_tests/I-LW-01.elf.hex similarity index 100% rename from src/riscv_tests/I-LW-01.elf.hex rename to emulator/riscv_tests/I-LW-01.elf.hex diff --git a/src/riscv_tests/I-MISALIGN_JMP-01.elf.hex b/emulator/riscv_tests/I-MISALIGN_JMP-01.elf.hex similarity index 100% rename from src/riscv_tests/I-MISALIGN_JMP-01.elf.hex rename to emulator/riscv_tests/I-MISALIGN_JMP-01.elf.hex diff --git a/src/riscv_tests/I-MISALIGN_LDST-01.elf.hex b/emulator/riscv_tests/I-MISALIGN_LDST-01.elf.hex similarity index 100% rename from src/riscv_tests/I-MISALIGN_LDST-01.elf.hex rename to emulator/riscv_tests/I-MISALIGN_LDST-01.elf.hex diff --git a/src/riscv_tests/I-NOP-01.elf.hex b/emulator/riscv_tests/I-NOP-01.elf.hex similarity index 100% rename from src/riscv_tests/I-NOP-01.elf.hex rename to emulator/riscv_tests/I-NOP-01.elf.hex diff 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src/riscv_tests/rv32ui-p-sltiu.hex rename to emulator/riscv_tests/rv32ui-p-sltiu.hex diff --git a/src/riscv_tests/rv32ui-p-sltu.hex b/emulator/riscv_tests/rv32ui-p-sltu.hex similarity index 100% rename from src/riscv_tests/rv32ui-p-sltu.hex rename to emulator/riscv_tests/rv32ui-p-sltu.hex diff --git a/src/riscv_tests/rv32ui-p-sra.hex b/emulator/riscv_tests/rv32ui-p-sra.hex similarity index 100% rename from src/riscv_tests/rv32ui-p-sra.hex rename to emulator/riscv_tests/rv32ui-p-sra.hex diff --git a/src/riscv_tests/rv32ui-p-srai.hex b/emulator/riscv_tests/rv32ui-p-srai.hex similarity index 100% rename from src/riscv_tests/rv32ui-p-srai.hex rename to emulator/riscv_tests/rv32ui-p-srai.hex diff --git a/src/riscv_tests/rv32ui-p-srl.hex b/emulator/riscv_tests/rv32ui-p-srl.hex similarity index 100% rename from src/riscv_tests/rv32ui-p-srl.hex rename to emulator/riscv_tests/rv32ui-p-srl.hex diff --git a/src/riscv_tests/rv32ui-p-srli.hex b/emulator/riscv_tests/rv32ui-p-srli.hex similarity index 100% rename from src/riscv_tests/rv32ui-p-srli.hex rename to emulator/riscv_tests/rv32ui-p-srli.hex diff --git a/src/riscv_tests/rv32ui-p-sub.hex b/emulator/riscv_tests/rv32ui-p-sub.hex similarity index 100% rename from src/riscv_tests/rv32ui-p-sub.hex rename to emulator/riscv_tests/rv32ui-p-sub.hex diff --git a/src/riscv_tests/rv32ui-p-sw.hex b/emulator/riscv_tests/rv32ui-p-sw.hex similarity index 100% rename from src/riscv_tests/rv32ui-p-sw.hex rename to emulator/riscv_tests/rv32ui-p-sw.hex diff --git a/src/riscv_tests/rv32ui-p-xor.hex b/emulator/riscv_tests/rv32ui-p-xor.hex similarity index 100% rename from src/riscv_tests/rv32ui-p-xor.hex rename to emulator/riscv_tests/rv32ui-p-xor.hex diff --git a/src/riscv_tests/rv32ui-p-xori.hex b/emulator/riscv_tests/rv32ui-p-xori.hex similarity index 100% rename from src/riscv_tests/rv32ui-p-xori.hex rename to emulator/riscv_tests/rv32ui-p-xori.hex diff --git a/src/riscv_tests/rv32um-p-div.hex b/emulator/riscv_tests/rv32um-p-div.hex similarity index 100% rename from src/riscv_tests/rv32um-p-div.hex rename to emulator/riscv_tests/rv32um-p-div.hex diff --git a/src/riscv_tests/rv32um-p-divu.hex b/emulator/riscv_tests/rv32um-p-divu.hex similarity index 100% rename from src/riscv_tests/rv32um-p-divu.hex rename to emulator/riscv_tests/rv32um-p-divu.hex diff --git a/src/riscv_tests/rv32um-p-mul.hex b/emulator/riscv_tests/rv32um-p-mul.hex similarity index 100% rename from src/riscv_tests/rv32um-p-mul.hex rename to emulator/riscv_tests/rv32um-p-mul.hex diff --git a/src/riscv_tests/rv32um-p-mulh.hex b/emulator/riscv_tests/rv32um-p-mulh.hex similarity index 100% rename from src/riscv_tests/rv32um-p-mulh.hex rename to emulator/riscv_tests/rv32um-p-mulh.hex diff --git a/src/riscv_tests/rv32um-p-mulhsu.hex b/emulator/riscv_tests/rv32um-p-mulhsu.hex similarity index 100% rename from src/riscv_tests/rv32um-p-mulhsu.hex rename to emulator/riscv_tests/rv32um-p-mulhsu.hex diff --git a/src/riscv_tests/rv32um-p-mulhu.hex b/emulator/riscv_tests/rv32um-p-mulhu.hex similarity index 100% rename from src/riscv_tests/rv32um-p-mulhu.hex rename to emulator/riscv_tests/rv32um-p-mulhu.hex diff --git a/src/riscv_tests/rv32um-p-rem.hex b/emulator/riscv_tests/rv32um-p-rem.hex similarity index 100% rename from src/riscv_tests/rv32um-p-rem.hex rename to emulator/riscv_tests/rv32um-p-rem.hex diff --git a/src/riscv_tests/rv32um-p-remu.hex b/emulator/riscv_tests/rv32um-p-remu.hex similarity index 100% rename from src/riscv_tests/rv32um-p-remu.hex rename to emulator/riscv_tests/rv32um-p-remu.hex diff --git a/src/riscv_tests/testA.hex b/emulator/riscv_tests/testA.hex similarity index 100% rename from src/riscv_tests/testA.hex rename to emulator/riscv_tests/testA.hex diff --git a/src/test.sh b/emulator/test.sh similarity index 100% rename from src/test.sh rename to emulator/test.sh diff --git a/emulator/test_riscv.sh b/emulator/test_riscv.sh new file mode 100755 index 00000000..96a7a446 --- /dev/null +++ b/emulator/test_riscv.sh @@ -0,0 +1,4 @@ +echo start > results.txt + +echo ../kernel/vortex_test.hex +./harptool -E -a rv32i --core ../kernel/vortex_test.hex -s -b diff --git a/src/util.cpp b/emulator/util.cpp similarity index 100% rename from src/util.cpp rename to emulator/util.cpp diff --git a/src/vortex_software/.DS_Store b/emulator/vortex_software/.DS_Store similarity index 100% rename from src/vortex_software/.DS_Store rename to emulator/vortex_software/.DS_Store diff --git a/src/vortex_software/Makefile b/emulator/vortex_software/Makefile similarity index 100% rename from src/vortex_software/Makefile rename to emulator/vortex_software/Makefile diff --git a/src/vortex_software/linker.ld b/emulator/vortex_software/linker.ld similarity index 100% rename from src/vortex_software/linker.ld rename to emulator/vortex_software/linker.ld diff --git a/src/vortex_software/vortex_test.dump b/emulator/vortex_software/vortex_test.dump similarity index 100% rename from src/vortex_software/vortex_test.dump rename to emulator/vortex_software/vortex_test.dump diff --git a/src/vortex_software/vortex_test.elf b/emulator/vortex_software/vortex_test.elf similarity index 100% rename from src/vortex_software/vortex_test.elf rename to emulator/vortex_software/vortex_test.elf diff --git a/src/vortex_software/vortex_test.hex b/emulator/vortex_software/vortex_test.hex similarity index 100% rename from src/vortex_software/vortex_test.hex rename to emulator/vortex_software/vortex_test.hex diff --git a/src/vortex_software/vx_include/.DS_Store b/emulator/vortex_software/vx_include/.DS_Store similarity index 100% rename from src/vortex_software/vx_include/.DS_Store rename to emulator/vortex_software/vx_include/.DS_Store diff --git a/src/vortex_software/vx_include/vx_front.c b/emulator/vortex_software/vx_include/vx_front.c similarity index 100% rename from src/vortex_software/vx_include/vx_front.c rename to emulator/vortex_software/vx_include/vx_front.c diff --git a/src/vortex_software/vx_include/vx_front.h b/emulator/vortex_software/vx_include/vx_front.h similarity index 100% rename from src/vortex_software/vx_include/vx_front.h rename to emulator/vortex_software/vx_include/vx_front.h diff --git a/src/vortex_software/vx_main.c b/emulator/vortex_software/vx_main.c similarity index 100% rename from src/vortex_software/vx_main.c rename to emulator/vortex_software/vx_main.c diff --git a/src/vortex_software/vx_os/.DS_Store b/emulator/vortex_software/vx_os/.DS_Store similarity index 100% rename from src/vortex_software/vx_os/.DS_Store rename to emulator/vortex_software/vx_os/.DS_Store diff --git a/src/vortex_software/vx_os/vx_back/vx_back.c b/emulator/vortex_software/vx_os/vx_back/vx_back.c similarity index 100% rename from src/vortex_software/vx_os/vx_back/vx_back.c rename to emulator/vortex_software/vx_os/vx_back/vx_back.c diff --git a/src/vortex_software/vx_os/vx_back/vx_back.h b/emulator/vortex_software/vx_os/vx_back/vx_back.h similarity index 100% rename from src/vortex_software/vx_os/vx_back/vx_back.h rename to emulator/vortex_software/vx_os/vx_back/vx_back.h diff --git a/src/vortex_software/vx_os/vx_back/vx_back.s b/emulator/vortex_software/vx_os/vx_back/vx_back.s similarity index 100% rename from src/vortex_software/vx_os/vx_back/vx_back.s rename to emulator/vortex_software/vx_os/vx_back/vx_back.s diff --git a/src/vortex_software/vx_os/vx_io/.DS_Store b/emulator/vortex_software/vx_os/vx_io/.DS_Store similarity index 100% rename from src/vortex_software/vx_os/vx_io/.DS_Store rename to emulator/vortex_software/vx_os/vx_io/.DS_Store diff --git a/src/vortex_software/vx_os/vx_io/vx_io.c b/emulator/vortex_software/vx_os/vx_io/vx_io.c similarity index 100% rename from src/vortex_software/vx_os/vx_io/vx_io.c rename to emulator/vortex_software/vx_os/vx_io/vx_io.c diff --git a/src/vortex_software/vx_os/vx_io/vx_io.h b/emulator/vortex_software/vx_os/vx_io/vx_io.h similarity index 100% rename from src/vortex_software/vx_os/vx_io/vx_io.h rename to emulator/vortex_software/vx_os/vx_io/vx_io.h diff --git a/src/vortex_software/vx_os/vx_io/vx_io.s b/emulator/vortex_software/vx_os/vx_io/vx_io.s similarity index 100% rename from src/vortex_software/vx_os/vx_io/vx_io.s rename to emulator/vortex_software/vx_os/vx_io/vx_io.s diff --git a/src/vortex_software/vx_os/vx_util/.DS_Store b/emulator/vortex_software/vx_os/vx_util/.DS_Store similarity index 100% rename from src/vortex_software/vx_os/vx_util/.DS_Store rename to emulator/vortex_software/vx_os/vx_util/.DS_Store diff --git a/src/vortex_software/vx_os/vx_util/queue.h b/emulator/vortex_software/vx_os/vx_util/queue.h similarity index 100% rename from src/vortex_software/vx_os/vx_util/queue.h rename to emulator/vortex_software/vx_os/vx_util/queue.h diff --git a/src/vortex_software/vx_os/vx_util/queue.s b/emulator/vortex_software/vx_os/vx_util/queue.s similarity index 100% rename from src/vortex_software/vx_os/vx_util/queue.s rename to emulator/vortex_software/vx_os/vx_util/queue.s diff --git a/kernel/.DS_Store b/kernel/.DS_Store new file mode 100644 index 00000000..8f25690d Binary files /dev/null and b/kernel/.DS_Store differ diff --git a/kernel/Makefile b/kernel/Makefile new file mode 100644 index 00000000..b82f85df --- /dev/null +++ b/kernel/Makefile @@ -0,0 +1,21 @@ + +COMP = /opt/riscv/bin/riscv32-unknown-elf-gcc +CC_FLAGS = -march=rv32im -mabi=ilp32 -O0 -Wl,-Bstatic,-T,linker.ld -ffreestanding -nostdlib + +DMP = /opt/riscv/bin/riscv32-unknown-elf-objdump +CPY = /opt/riscv/bin/riscv32-unknown-elf-objcopy + +VX_LIB = ./vx_os/vx_back/vx_back.s ./vx_os/vx_back/vx_back.c ./vx_os/vx_util/queue.s +VX_IO = ./vx_os/vx_io/vx_io.s ./vx_os/vx_io/vx_io.c +VX_FR = ./vx_include/vx_front.c + +all: HEX DUMP ELF + +DUMP: ELF + $(DMP) -D vortex_test.elf > vortex_test.dump + +HEX: ELF + $(CPY) -O ihex vortex_test.elf vortex_test.hex + +ELF: + $(COMP) $(CC_FLAGS) $(VX_LIB) $(VX_IO) $(VX_FR) vx_main.c -o vortex_test.elf diff --git a/kernel/linker.ld b/kernel/linker.ld new file mode 100644 index 00000000..8fbf7896 --- /dev/null +++ b/kernel/linker.ld @@ -0,0 +1,48 @@ +/* ---- Original Script: /opt/riscv32i/riscv32-unknown-elf/lib/ldscripts/elf32lriscv.x ---- */ +/* Default linker script, for normal executables */ +/* Copyright (C) 2014-2017 Free Software Foundation, Inc. + Copying and distribution of this script, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. */ +OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", + "elf32-littleriscv") +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS +{ + . = 0x80000000; + .text : + { + *(.text) + *(.text.unlikely .text.*_unlikely .text.unlikely.*) + *(.text.exit .text.exit.*) + *(.text.startup .text.startup.*) + *(.text.hot .text.hot.*) + *(.stub .text.* .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } + .init : + { + KEEP (*(SORT_NONE(.init))) + } + .plt : { *(.plt) } + .iplt : { *(.iplt) } + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + PROVIDE (_edata = .); + PROVIDE (_end = .); + PROVIDE (__global_pointer$ = .); + + . = 0x81000000; + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } + .rodata1 : { *(.rodata1) } + . = 0x82000000; + .comment : { *(.comment) } + +} diff --git a/kernel/vortex_test.dump b/kernel/vortex_test.dump new file mode 100644 index 00000000..672a1437 --- /dev/null +++ b/kernel/vortex_test.dump @@ -0,0 +1,2067 @@ + +vortex_test.elf: file format elf32-littleriscv + + +Disassembly of section .text: + +80000000 <_start>: +80000000: 00400513 li a0,4 +80000004: 02051073 csrw 0x20,a0 +80000008: 00800513 li a0,8 +8000000c: 02151073 csrw 0x21,a0 +80000010: f1401073 csrw mhartid,zero +80000014: 30101073 csrw misa,zero +80000018: 7ffff137 lui sp,0x7ffff +8000001c: 198000ef jal ra,800001b4 +80000020: 6dc010ef jal ra,800016fc
+80000024: 00000073 ecall + +80000028 : +80000028: 00068b93 mv s7,a3 +8000002c: 00070d13 mv s10,a4 +80000030: 00010f13 mv t5,sp +80000034: 00050393 mv t2,a0 + +80000038 : +80000038: 00100513 li a0,1 + +8000003c : +8000003c: 00755c63 bge a0,t2,80000054 + +80000040 : +80000040: 80010113 addi sp,sp,-2048 # 7fffe800 +80000044: 00050313 mv t1,a0 +80000048: 0003506b 0x3506b + +8000004c : +8000004c: 00150513 addi a0,a0,1 +80000050: fedff06f j 8000003c + +80000054 : +80000054: 000f0113 mv sp,t5 +80000058: 00000513 li a0,0 +8000005c: 00060f93 mv t6,a2 +80000060: 00038d93 mv s11,t2 +80000064: 01bfe0eb 0x1bfe0eb +80000068: 00000517 auipc a0,0x0 +8000006c: 1b050513 addi a0,a0,432 # 80000218 +80000070: 0005406b 0x5406b + +80000074 : +80000074: 00000317 auipc t1,0x0 +80000078: fb430313 addi t1,t1,-76 # 80000028 +8000007c: 0003006b 0x3006b +80000080: 00008067 ret + +80000084 : +80000084: 01000217 auipc tp,0x1000 +80000088: 26020213 addi tp,tp,608 # 810002e4 +8000008c: 00022023 sw zero,0(tp) # 0 +80000090: 00122223 sw ra,4(tp) # 4 +80000094: 00222423 sw sp,8(tp) # 8 +80000098: 00322623 sw gp,12(tp) # c +8000009c: 00422823 sw tp,16(tp) # 10 +800000a0: 00522a23 sw t0,20(tp) # 14 +800000a4: 00622c23 sw t1,24(tp) # 18 +800000a8: 00722e23 sw t2,28(tp) # 1c +800000ac: 02822023 sw s0,32(tp) # 20 +800000b0: 02922223 sw s1,36(tp) # 24 +800000b4: 02a22423 sw a0,40(tp) # 28 +800000b8: 02b22623 sw a1,44(tp) # 2c +800000bc: 02c22823 sw a2,48(tp) # 30 +800000c0: 02d22a23 sw a3,52(tp) # 34 +800000c4: 02e22c23 sw a4,56(tp) # 38 +800000c8: 02f22e23 sw a5,60(tp) # 3c +800000cc: 05022023 sw a6,64(tp) # 40 +800000d0: 05122223 sw a7,68(tp) # 44 +800000d4: 05222423 sw s2,72(tp) # 48 +800000d8: 05322623 sw s3,76(tp) # 4c +800000dc: 05422823 sw s4,80(tp) # 50 +800000e0: 05522a23 sw s5,84(tp) # 54 +800000e4: 05622c23 sw s6,88(tp) # 58 +800000e8: 05722e23 sw s7,92(tp) # 5c +800000ec: 07822023 sw s8,96(tp) # 60 +800000f0: 07922223 sw s9,100(tp) # 64 +800000f4: 07a22423 sw s10,104(tp) # 68 +800000f8: 07b22623 sw s11,108(tp) # 6c +800000fc: 07c22823 sw t3,112(tp) # 70 +80000100: 07d22a23 sw t4,116(tp) # 74 +80000104: 07e22c23 sw t5,120(tp) # 78 +80000108: 07f22e23 sw t6,124(tp) # 7c +8000010c: 00100213 li tp,1 +80000110: 00008067 ret + +80000114 : +80000114: 01000217 auipc tp,0x1000 +80000118: 1d020213 addi tp,tp,464 # 810002e4 +8000011c: 00022003 lw zero,0(tp) # 0 +80000120: 00422083 lw ra,4(tp) # 4 +80000124: 00822103 lw sp,8(tp) # 8 +80000128: 00c22183 lw gp,12(tp) # c +8000012c: 01022203 lw tp,16(tp) # 10 +80000130: 01422283 lw t0,20(tp) # 14 +80000134: 01822303 lw t1,24(tp) # 18 +80000138: 01c22383 lw t2,28(tp) # 1c +8000013c: 02022403 lw s0,32(tp) # 20 +80000140: 02422483 lw s1,36(tp) # 24 +80000144: 02822503 lw a0,40(tp) # 28 +80000148: 02c22583 lw a1,44(tp) # 2c +8000014c: 03022603 lw a2,48(tp) # 30 +80000150: 03422683 lw a3,52(tp) # 34 +80000154: 03822703 lw a4,56(tp) # 38 +80000158: 03c22783 lw a5,60(tp) # 3c +8000015c: 04022803 lw a6,64(tp) # 40 +80000160: 04422883 lw a7,68(tp) # 44 +80000164: 04822903 lw s2,72(tp) # 48 +80000168: 04c22983 lw s3,76(tp) # 4c +8000016c: 05022a03 lw s4,80(tp) # 50 +80000170: 05422a83 lw s5,84(tp) # 54 +80000174: 05822b03 lw s6,88(tp) # 58 +80000178: 05c22b83 lw s7,92(tp) # 5c +8000017c: 06022c03 lw s8,96(tp) # 60 +80000180: 06422c83 lw s9,100(tp) # 64 +80000184: 06822d03 lw s10,104(tp) # 68 +80000188: 06c22d83 lw s11,108(tp) # 6c +8000018c: 07022e03 lw t3,112(tp) # 70 +80000190: 07422e83 lw t4,116(tp) # 74 +80000194: 07822f03 lw t5,120(tp) # 78 +80000198: 07c22f83 lw t6,124(tp) # 7c +8000019c: 00000213 li tp,0 +800001a0: 00008067 ret + +800001a4 : +800001a4: 02002573 csrr a0,0x20 +800001a8: 00008067 ret + +800001ac : +800001ac: 02102573 csrr a0,0x21 +800001b0: 00008067 ret + +800001b4 : +800001b4: fe010113 addi sp,sp,-32 +800001b8: 00112e23 sw ra,28(sp) +800001bc: 00812c23 sw s0,24(sp) +800001c0: 02010413 addi s0,sp,32 +800001c4: fe042623 sw zero,-20(s0) +800001c8: 0300006f j 800001f8 +800001cc: fec42703 lw a4,-20(s0) +800001d0: 4c400793 li a5,1220 +800001d4: 02f70733 mul a4,a4,a5 +800001d8: 810007b7 lui a5,0x81000 +800001dc: 36478793 addi a5,a5,868 # 81000364 +800001e0: 00f707b3 add a5,a4,a5 +800001e4: 00078513 mv a0,a5 +800001e8: 404000ef jal ra,800005ec +800001ec: fec42783 lw a5,-20(s0) +800001f0: 00178793 addi a5,a5,1 +800001f4: fef42623 sw a5,-20(s0) +800001f8: fec42703 lw a4,-20(s0) +800001fc: 00700793 li a5,7 +80000200: fce7d6e3 bge a5,a4,800001cc +80000204: 00000013 nop +80000208: 01c12083 lw ra,28(sp) +8000020c: 01812403 lw s0,24(sp) +80000210: 02010113 addi sp,sp,32 +80000214: 00008067 ret + +80000218 : +80000218: fd010113 addi sp,sp,-48 +8000021c: 02112623 sw ra,44(sp) +80000220: 02812423 sw s0,40(sp) +80000224: 03a12223 sw s10,36(sp) +80000228: 03010413 addi s0,sp,48 +8000022c: 000d0713 mv a4,s10 +80000230: 4c400793 li a5,1220 +80000234: 02f70733 mul a4,a4,a5 +80000238: 810007b7 lui a5,0x81000 +8000023c: 36478793 addi a5,a5,868 # 81000364 +80000240: 00f707b3 add a5,a4,a5 +80000244: 00078513 mv a0,a5 +80000248: 4b8000ef jal ra,80000700 +8000024c: 00050793 mv a5,a0 +80000250: 02078a63 beqz a5,80000284 +80000254: 000d0713 mv a4,s10 +80000258: 810007b7 lui a5,0x81000 +8000025c: 00271713 slli a4,a4,0x2 +80000260: 2c478793 addi a5,a5,708 # 810002c4 +80000264: 00f707b3 add a5,a4,a5 +80000268: 00100713 li a4,1 +8000026c: 00e7a023 sw a4,0(a5) +80000270: 000d0793 mv a5,s10 +80000274: 00079663 bnez a5,80000280 +80000278: e9dff0ef jal ra,80000114 +8000027c: 0580006f j 800002d4 +80000280: 00000073 ecall +80000284: 000d0713 mv a4,s10 +80000288: 4c400793 li a5,1220 +8000028c: 02f70733 mul a4,a4,a5 +80000290: 810007b7 lui a5,0x81000 +80000294: 36478793 addi a5,a5,868 # 81000364 +80000298: 00f707b3 add a5,a4,a5 +8000029c: fd840713 addi a4,s0,-40 +800002a0: 00070593 mv a1,a4 +800002a4: 00078513 mv a0,a5 +800002a8: 3d0000ef jal ra,80000678 +800002ac: fe042783 lw a5,-32(s0) +800002b0: 00078113 mv sp,a5 +800002b4: fdc42783 lw a5,-36(s0) +800002b8: fd842583 lw a1,-40(s0) +800002bc: fe442603 lw a2,-28(s0) +800002c0: fe842683 lw a3,-24(s0) +800002c4: fec42703 lw a4,-20(s0) +800002c8: 00078513 mv a0,a5 +800002cc: d5dff0ef jal ra,80000028 +800002d0: 00000073 ecall +800002d4: 02c12083 lw ra,44(sp) +800002d8: 02812403 lw s0,40(sp) +800002dc: 02412d03 lw s10,36(sp) +800002e0: 03010113 addi sp,sp,48 +800002e4: 00008067 ret + +800002e8 : +800002e8: fb010113 addi sp,sp,-80 +800002ec: 04112623 sw ra,76(sp) +800002f0: 04812423 sw s0,72(sp) +800002f4: 05010413 addi s0,sp,80 +800002f8: eadff0ef jal ra,800001a4 +800002fc: fea42423 sw a0,-24(s0) +80000300: 00010993 mv s3,sp +80000304: 00100793 li a5,1 +80000308: fef42623 sw a5,-20(s0) +8000030c: 0840006f j 80000390 +80000310: fec42703 lw a4,-20(s0) +80000314: 4c400793 li a5,1220 +80000318: 02f70733 mul a4,a4,a5 +8000031c: 810007b7 lui a5,0x81000 +80000320: 36478793 addi a5,a5,868 # 81000364 +80000324: 00f707b3 add a5,a4,a5 +80000328: 00078513 mv a0,a5 +8000032c: 3d4000ef jal ra,80000700 +80000330: 00050793 mv a5,a0 +80000334: 04079863 bnez a5,80000384 +80000338: fec42703 lw a4,-20(s0) +8000033c: 4c400793 li a5,1220 +80000340: 02f70733 mul a4,a4,a5 +80000344: 810007b7 lui a5,0x81000 +80000348: 36478793 addi a5,a5,868 # 81000364 +8000034c: 00f707b3 add a5,a4,a5 +80000350: fd040713 addi a4,s0,-48 +80000354: 00070593 mv a1,a4 +80000358: 00078513 mv a0,a5 +8000035c: 31c000ef jal ra,80000678 +80000360: fd842783 lw a5,-40(s0) +80000364: 00078113 mv sp,a5 +80000368: fd442783 lw a5,-44(s0) +8000036c: fd042583 lw a1,-48(s0) +80000370: fdc42603 lw a2,-36(s0) +80000374: fe042683 lw a3,-32(s0) +80000378: fe442703 lw a4,-28(s0) +8000037c: 00078513 mv a0,a5 +80000380: cf5ff0ef jal ra,80000074 +80000384: fec42783 lw a5,-20(s0) +80000388: 00178793 addi a5,a5,1 +8000038c: fef42623 sw a5,-20(s0) +80000390: fec42783 lw a5,-20(s0) +80000394: fe842703 lw a4,-24(s0) +80000398: f6e7ece3 bltu a5,a4,80000310 +8000039c: 00098113 mv sp,s3 +800003a0: ce5ff0ef jal ra,80000084 +800003a4: 00020793 mv a5,tp +800003a8: 04078863 beqz a5,800003f8 +800003ac: 810007b7 lui a5,0x81000 +800003b0: 36478513 addi a0,a5,868 # 81000364 +800003b4: 34c000ef jal ra,80000700 +800003b8: 00050793 mv a5,a0 +800003bc: 02079e63 bnez a5,800003f8 +800003c0: fb840793 addi a5,s0,-72 +800003c4: 00078593 mv a1,a5 +800003c8: 810007b7 lui a5,0x81000 +800003cc: 36478513 addi a0,a5,868 # 81000364 +800003d0: 2a8000ef jal ra,80000678 +800003d4: fc042783 lw a5,-64(s0) +800003d8: 00078113 mv sp,a5 +800003dc: fbc42783 lw a5,-68(s0) +800003e0: fb842583 lw a1,-72(s0) +800003e4: fc442603 lw a2,-60(s0) +800003e8: fc842683 lw a3,-56(s0) +800003ec: fcc42703 lw a4,-52(s0) +800003f0: 00078513 mv a0,a5 +800003f4: c35ff0ef jal ra,80000028 +800003f8: 00000013 nop +800003fc: 04c12083 lw ra,76(sp) +80000400: 04812403 lw s0,72(sp) +80000404: 05010113 addi sp,sp,80 +80000408: 00008067 ret + +8000040c : +8000040c: fb010113 addi sp,sp,-80 +80000410: 04112623 sw ra,76(sp) +80000414: 04812423 sw s0,72(sp) +80000418: 05010413 addi s0,sp,80 +8000041c: faa42e23 sw a0,-68(s0) +80000420: fab42c23 sw a1,-72(s0) +80000424: fac42a23 sw a2,-76(s0) +80000428: fad42823 sw a3,-80(s0) +8000042c: d89ff0ef jal ra,800001b4 +80000430: d75ff0ef jal ra,800001a4 +80000434: fea42223 sw a0,-28(s0) +80000438: 00010913 mv s2,sp +8000043c: fe042623 sw zero,-20(s0) +80000440: fe042423 sw zero,-24(s0) +80000444: 08c0006f j 800004d0 +80000448: ffff09b7 lui s3,0xffff0 +8000044c: 01310133 add sp,sp,s3 +80000450: fe842783 lw a5,-24(s0) +80000454: fcf42623 sw a5,-52(s0) +80000458: fb842783 lw a5,-72(s0) +8000045c: fcf42823 sw a5,-48(s0) +80000460: 00010793 mv a5,sp +80000464: fcf42a23 sw a5,-44(s0) +80000468: fb442783 lw a5,-76(s0) +8000046c: fcf42c23 sw a5,-40(s0) +80000470: fb042783 lw a5,-80(s0) +80000474: fcf42e23 sw a5,-36(s0) +80000478: fec42783 lw a5,-20(s0) +8000047c: fef42023 sw a5,-32(s0) +80000480: fec42703 lw a4,-20(s0) +80000484: 4c400793 li a5,1220 +80000488: 02f70733 mul a4,a4,a5 +8000048c: 810007b7 lui a5,0x81000 +80000490: 36478793 addi a5,a5,868 # 81000364 +80000494: 00f707b3 add a5,a4,a5 +80000498: fcc40713 addi a4,s0,-52 +8000049c: 00070593 mv a1,a4 +800004a0: 00078513 mv a0,a5 +800004a4: 16c000ef jal ra,80000610 +800004a8: fec42783 lw a5,-20(s0) +800004ac: 00178793 addi a5,a5,1 +800004b0: fef42623 sw a5,-20(s0) +800004b4: fec42783 lw a5,-20(s0) +800004b8: fe442703 lw a4,-28(s0) +800004bc: 00e7e463 bltu a5,a4,800004c4 +800004c0: fe042623 sw zero,-20(s0) +800004c4: fe842783 lw a5,-24(s0) +800004c8: 00178793 addi a5,a5,1 +800004cc: fef42423 sw a5,-24(s0) +800004d0: fe842703 lw a4,-24(s0) +800004d4: fbc42783 lw a5,-68(s0) +800004d8: f6f768e3 bltu a4,a5,80000448 +800004dc: 00090113 mv sp,s2 +800004e0: e09ff0ef jal ra,800002e8 +800004e4: 00000013 nop +800004e8: 04c12083 lw ra,76(sp) +800004ec: 04812403 lw s0,72(sp) +800004f0: 05010113 addi sp,sp,80 +800004f4: 00008067 ret + +800004f8 : +800004f8: fd010113 addi sp,sp,-48 +800004fc: 02112623 sw ra,44(sp) +80000500: 02812423 sw s0,40(sp) +80000504: 03010413 addi s0,sp,48 +80000508: fca42e23 sw a0,-36(s0) +8000050c: c99ff0ef jal ra,800001a4 +80000510: fea42023 sw a0,-32(s0) +80000514: fe042623 sw zero,-20(s0) +80000518: 0540006f j 8000056c +8000051c: fe042623 sw zero,-20(s0) +80000520: fe042423 sw zero,-24(s0) +80000524: 03c0006f j 80000560 +80000528: 810007b7 lui a5,0x81000 +8000052c: fe842703 lw a4,-24(s0) +80000530: 00271713 slli a4,a4,0x2 +80000534: 2c478793 addi a5,a5,708 # 810002c4 +80000538: 00f707b3 add a5,a4,a5 +8000053c: 0007a703 lw a4,0(a5) +80000540: 00100793 li a5,1 +80000544: 00f71863 bne a4,a5,80000554 +80000548: fec42783 lw a5,-20(s0) +8000054c: 00178793 addi a5,a5,1 +80000550: fef42623 sw a5,-20(s0) +80000554: fe842783 lw a5,-24(s0) +80000558: 00178793 addi a5,a5,1 +8000055c: fef42423 sw a5,-24(s0) +80000560: fe842783 lw a5,-24(s0) +80000564: fe042703 lw a4,-32(s0) +80000568: fce7e0e3 bltu a5,a4,80000528 +8000056c: fec42703 lw a4,-20(s0) +80000570: fdc42783 lw a5,-36(s0) +80000574: faf714e3 bne a4,a5,8000051c +80000578: fe042223 sw zero,-28(s0) +8000057c: 0280006f j 800005a4 +80000580: 810007b7 lui a5,0x81000 +80000584: fe442703 lw a4,-28(s0) +80000588: 00271713 slli a4,a4,0x2 +8000058c: 2c478793 addi a5,a5,708 # 810002c4 +80000590: 00f707b3 add a5,a4,a5 +80000594: 0007a023 sw zero,0(a5) +80000598: fe442783 lw a5,-28(s0) +8000059c: 00178793 addi a5,a5,1 +800005a0: fef42223 sw a5,-28(s0) +800005a4: fe442783 lw a5,-28(s0) +800005a8: fe042703 lw a4,-32(s0) +800005ac: fce7eae3 bltu a5,a4,80000580 +800005b0: 00000013 nop +800005b4: 02c12083 lw ra,44(sp) +800005b8: 02812403 lw s0,40(sp) +800005bc: 03010113 addi sp,sp,48 +800005c0: 00008067 ret + +800005c4 : +800005c4: ff010113 addi sp,sp,-16 +800005c8: 00812623 sw s0,12(sp) +800005cc: 01712423 sw s7,8(sp) +800005d0: 01010413 addi s0,sp,16 +800005d4: 000b8793 mv a5,s7 +800005d8: 00078513 mv a0,a5 +800005dc: 00c12403 lw s0,12(sp) +800005e0: 00812b83 lw s7,8(sp) +800005e4: 01010113 addi sp,sp,16 +800005e8: 00008067 ret + +800005ec : +800005ec: 00050293 mv t0,a0 +800005f0: 00000313 li t1,0 +800005f4: 00700393 li t2,7 +800005f8: 0062a023 sw t1,0(t0) +800005fc: 0062a223 sw t1,4(t0) +80000600: 0062a423 sw t1,8(t0) +80000604: 0072a623 sw t2,12(t0) +80000608: 0062a823 sw t1,16(t0) +8000060c: 00008067 ret + +80000610 : +80000610: 00050293 mv t0,a0 +80000614: 0082a303 lw t1,8(t0) +80000618: 00130313 addi t1,t1,1 +8000061c: 0062a423 sw t1,8(t0) +80000620: 01428313 addi t1,t0,20 +80000624: 0042ae83 lw t4,4(t0) +80000628: 005e9393 slli t2,t4,0x5 +8000062c: 00730333 add t1,t1,t2 +80000630: 0005ae03 lw t3,0(a1) +80000634: 01c32023 sw t3,0(t1) +80000638: 0045ae03 lw t3,4(a1) +8000063c: 01c32223 sw t3,4(t1) +80000640: 0085ae03 lw t3,8(a1) +80000644: 01c32423 sw t3,8(t1) +80000648: 00c5ae03 lw t3,12(a1) +8000064c: 01c32623 sw t3,12(t1) +80000650: 0105ae03 lw t3,16(a1) +80000654: 01c32823 sw t3,16(t1) +80000658: 0145ae03 lw t3,20(a1) +8000065c: 01c32a23 sw t3,20(t1) +80000660: 001e8e93 addi t4,t4,1 +80000664: 03200f13 li t5,50 +80000668: 01ee9463 bne t4,t5,80000670 +8000066c: 00000e93 li t4,0 + +80000670 : +80000670: 01d2a223 sw t4,4(t0) +80000674: 00008067 ret + +80000678 : +80000678: 00050293 mv t0,a0 +8000067c: 0082a303 lw t1,8(t0) +80000680: fff30313 addi t1,t1,-1 +80000684: 0062a423 sw t1,8(t0) +80000688: 01428313 addi t1,t0,20 +8000068c: 0002ae83 lw t4,0(t0) +80000690: 03200f93 li t6,50 +80000694: 000e8f13 mv t5,t4 +80000698: 001f0f13 addi t5,t5,1 +8000069c: 01ff1463 bne t5,t6,800006a4 +800006a0: 00000f13 li t5,0 + +800006a4 : +800006a4: 01e2a023 sw t5,0(t0) +800006a8: 005e9393 slli t2,t4,0x5 +800006ac: 00730333 add t1,t1,t2 +800006b0: 00032e03 lw t3,0(t1) +800006b4: 01c5a023 sw t3,0(a1) +800006b8: 00432e03 lw t3,4(t1) +800006bc: 01c5a223 sw t3,4(a1) +800006c0: 00832e03 lw t3,8(t1) +800006c4: 01c5a423 sw t3,8(a1) +800006c8: 00c32e03 lw t3,12(t1) +800006cc: 01c5a623 sw t3,12(a1) +800006d0: 01032e03 lw t3,16(t1) +800006d4: 01c5a823 sw t3,16(a1) +800006d8: 01432e03 lw t3,20(t1) +800006dc: 01c5aa23 sw t3,20(a1) +800006e0: 00008067 ret + +800006e4 : +800006e4: 00050293 mv t0,a0 +800006e8: 0082a303 lw t1,8(t0) +800006ec: 00000513 li a0,0 +800006f0: 03200e13 li t3,50 +800006f4: 006e1463 bne t3,t1,800006fc +800006f8: 00150513 addi a0,a0,1 + +800006fc : +800006fc: 00008067 ret + +80000700 : +80000700: 00050293 mv t0,a0 +80000704: 0082a303 lw t1,8(t0) +80000708: 00000513 li a0,0 +8000070c: 00000e13 li t3,0 +80000710: 006e1463 bne t3,t1,80000718 +80000714: 00150513 addi a0,a0,1 + +80000718 : +80000718: 00008067 ret + +8000071c : +8000071c: 00050293 mv t0,a0 +80000720: 00c2a303 lw t1,12(t0) +80000724: 0102a383 lw t2,16(t0) +80000728: 0063b533 sltu a0,t2,t1 +8000072c: 00008067 ret + +80000730 : +80000730: ff410113 addi sp,sp,-12 +80000734: 00112023 sw ra,0(sp) +80000738: 00b12223 sw a1,4(sp) + +8000073c : +8000073c: 00054583 lbu a1,0(a0) +80000740: 00058863 beqz a1,80000750 +80000744: 01c000ef jal ra,80000760 +80000748: 00150513 addi a0,a0,1 +8000074c: ff1ff06f j 8000073c + +80000750 : +80000750: 00012083 lw ra,0(sp) +80000754: 00412583 lw a1,4(sp) +80000758: 00c10113 addi sp,sp,12 +8000075c: 00008067 ret + +80000760 : +80000760: 000108b7 lui a7,0x10 +80000764: 00b8a023 sw a1,0(a7) # 10000 +80000768: 00008067 ret + +8000076c : +8000076c: fd010113 addi sp,sp,-48 +80000770: 02112623 sw ra,44(sp) +80000774: 02812423 sw s0,40(sp) +80000778: 03010413 addi s0,sp,48 +8000077c: fca42e23 sw a0,-36(s0) +80000780: fdc42703 lw a4,-36(s0) +80000784: 00f00793 li a5,15 +80000788: 02e7e463 bltu a5,a4,800007b0 +8000078c: 810007b7 lui a5,0x81000 +80000790: fdc42703 lw a4,-36(s0) +80000794: 00271713 slli a4,a4,0x2 +80000798: 20478793 addi a5,a5,516 # 81000204 +8000079c: 00f707b3 add a5,a4,a5 +800007a0: 0007a783 lw a5,0(a5) +800007a4: 00078513 mv a0,a5 +800007a8: f89ff0ef jal ra,80000730 +800007ac: 0740006f j 80000820 +800007b0: 02000793 li a5,32 +800007b4: fef42623 sw a5,-20(s0) +800007b8: fe0405a3 sb zero,-21(s0) +800007bc: fec42783 lw a5,-20(s0) +800007c0: ffc78793 addi a5,a5,-4 +800007c4: fdc42703 lw a4,-36(s0) +800007c8: 00f757b3 srl a5,a4,a5 +800007cc: 00f7f793 andi a5,a5,15 +800007d0: fef42223 sw a5,-28(s0) +800007d4: fe442783 lw a5,-28(s0) +800007d8: 00078663 beqz a5,800007e4 +800007dc: 00100793 li a5,1 +800007e0: fef405a3 sb a5,-21(s0) +800007e4: feb44783 lbu a5,-21(s0) +800007e8: 02078263 beqz a5,8000080c +800007ec: 810007b7 lui a5,0x81000 +800007f0: fe442703 lw a4,-28(s0) +800007f4: 00271713 slli a4,a4,0x2 +800007f8: 20478793 addi a5,a5,516 # 81000204 +800007fc: 00f707b3 add a5,a4,a5 +80000800: 0007a783 lw a5,0(a5) +80000804: 00078513 mv a0,a5 +80000808: f29ff0ef jal ra,80000730 +8000080c: fec42783 lw a5,-20(s0) +80000810: ffc78793 addi a5,a5,-4 +80000814: fef42623 sw a5,-20(s0) +80000818: fec42783 lw a5,-20(s0) +8000081c: faf040e3 bgtz a5,800007bc +80000820: 02c12083 lw ra,44(sp) +80000824: 02812403 lw s0,40(sp) +80000828: 03010113 addi sp,sp,48 +8000082c: 00008067 ret + +80000830 : +80000830: fe010113 addi sp,sp,-32 +80000834: 00112e23 sw ra,28(sp) +80000838: 00812c23 sw s0,24(sp) +8000083c: 02010413 addi s0,sp,32 +80000840: fea42623 sw a0,-20(s0) +80000844: feb42423 sw a1,-24(s0) +80000848: fec42503 lw a0,-20(s0) +8000084c: ee5ff0ef jal ra,80000730 +80000850: fe842503 lw a0,-24(s0) +80000854: f19ff0ef jal ra,8000076c +80000858: 810007b7 lui a5,0x81000 +8000085c: 08078513 addi a0,a5,128 # 81000080 +80000860: ed1ff0ef jal ra,80000730 +80000864: 00000013 nop +80000868: 01c12083 lw ra,28(sp) +8000086c: 01812403 lw s0,24(sp) +80000870: 02010113 addi sp,sp,32 +80000874: 00008067 ret + +80000878 : +80000878: fd010113 addi sp,sp,-48 +8000087c: 02112623 sw ra,44(sp) +80000880: 02812423 sw s0,40(sp) +80000884: 03010413 addi s0,sp,48 +80000888: fca42e23 sw a0,-36(s0) +8000088c: fcb42c23 sw a1,-40(s0) +80000890: fcc42a23 sw a2,-44(s0) +80000894: fcd42823 sw a3,-48(s0) +80000898: 810037b7 lui a5,0x81003 +8000089c: fdc42703 lw a4,-36(s0) +800008a0: 9ae7a223 sw a4,-1628(a5) # 810029a4 +800008a4: 810037b7 lui a5,0x81003 +800008a8: 9a478793 addi a5,a5,-1628 # 810029a4 +800008ac: fd842703 lw a4,-40(s0) +800008b0: 00e7a223 sw a4,4(a5) +800008b4: 810037b7 lui a5,0x81003 +800008b8: 9a478793 addi a5,a5,-1628 # 810029a4 +800008bc: fd442703 lw a4,-44(s0) +800008c0: 00e7a423 sw a4,8(a5) +800008c4: 810037b7 lui a5,0x81003 +800008c8: 9a478793 addi a5,a5,-1628 # 810029a4 +800008cc: fd042703 lw a4,-48(s0) +800008d0: 00e7a623 sw a4,12(a5) +800008d4: 8d9ff0ef jal ra,800001ac +800008d8: fea42423 sw a0,-24(s0) +800008dc: fd042703 lw a4,-48(s0) +800008e0: fe842783 lw a5,-24(s0) +800008e4: 02f757b3 divu a5,a4,a5 +800008e8: fef42623 sw a5,-20(s0) +800008ec: fd042703 lw a4,-48(s0) +800008f0: fe842783 lw a5,-24(s0) +800008f4: 02f777b3 remu a5,a4,a5 +800008f8: 00078863 beqz a5,80000908 +800008fc: fec42783 lw a5,-20(s0) +80000900: 00178793 addi a5,a5,1 +80000904: fef42623 sw a5,-20(s0) +80000908: fec42583 lw a1,-20(s0) +8000090c: 810007b7 lui a5,0x81000 +80000910: 0c478513 addi a0,a5,196 # 810000c4 +80000914: f1dff0ef jal ra,80000830 +80000918: 810037b7 lui a5,0x81003 +8000091c: 9a478793 addi a5,a5,-1628 # 810029a4 +80000920: fec42703 lw a4,-20(s0) +80000924: 00e7a823 sw a4,16(a5) +80000928: fd042703 lw a4,-48(s0) +8000092c: fe842783 lw a5,-24(s0) +80000930: 02f76263 bltu a4,a5,80000954 +80000934: 810037b7 lui a5,0x81003 +80000938: 9a478693 addi a3,a5,-1628 # 810029a4 +8000093c: 800017b7 lui a5,0x80001 +80000940: 9ac78613 addi a2,a5,-1620 # 800009ac +80000944: fe842583 lw a1,-24(s0) +80000948: fd042503 lw a0,-48(s0) +8000094c: ac1ff0ef jal ra,8000040c +80000950: 0200006f j 80000970 +80000954: 810037b7 lui a5,0x81003 +80000958: 9a478693 addi a3,a5,-1628 # 810029a4 +8000095c: 800017b7 lui a5,0x80001 +80000960: 9ac78613 addi a2,a5,-1620 # 800009ac +80000964: fd042583 lw a1,-48(s0) +80000968: fd042503 lw a0,-48(s0) +8000096c: aa1ff0ef jal ra,8000040c +80000970: 835ff0ef jal ra,800001a4 +80000974: fea42223 sw a0,-28(s0) +80000978: fd042703 lw a4,-48(s0) +8000097c: fe442783 lw a5,-28(s0) +80000980: 00e7f863 bgeu a5,a4,80000990 +80000984: fe442503 lw a0,-28(s0) +80000988: b71ff0ef jal ra,800004f8 +8000098c: 00c0006f j 80000998 +80000990: fd042503 lw a0,-48(s0) +80000994: b65ff0ef jal ra,800004f8 +80000998: 00000013 nop +8000099c: 02c12083 lw ra,44(sp) +800009a0: 02812403 lw s0,40(sp) +800009a4: 03010113 addi sp,sp,48 +800009a8: 00008067 ret + +800009ac <_vx_mat_mult>: +800009ac: fa010113 addi sp,sp,-96 +800009b0: 04112e23 sw ra,92(sp) +800009b4: 04812c23 sw s0,88(sp) +800009b8: 06010413 addi s0,sp,96 +800009bc: faa42623 sw a0,-84(s0) +800009c0: fab42423 sw a1,-88(s0) +800009c4: c01ff0ef jal ra,800005c4 +800009c8: fca42c23 sw a0,-40(s0) +800009cc: fd842783 lw a5,-40(s0) +800009d0: 0007a783 lw a5,0(a5) +800009d4: fcf42a23 sw a5,-44(s0) +800009d8: fd842783 lw a5,-40(s0) +800009dc: 0047a783 lw a5,4(a5) +800009e0: fcf42823 sw a5,-48(s0) +800009e4: fd842783 lw a5,-40(s0) +800009e8: 0087a783 lw a5,8(a5) +800009ec: fcf42623 sw a5,-52(s0) +800009f0: fd842783 lw a5,-40(s0) +800009f4: 0107a783 lw a5,16(a5) +800009f8: fef42623 sw a5,-20(s0) +800009fc: fec42703 lw a4,-20(s0) +80000a00: fac42783 lw a5,-84(s0) +80000a04: 02f707b3 mul a5,a4,a5 +80000a08: fef42423 sw a5,-24(s0) +80000a0c: fec42783 lw a5,-20(s0) +80000a10: 00079a63 bnez a5,80000a24 <_vx_mat_mult+0x78> +80000a14: 00100793 li a5,1 +80000a18: fef42623 sw a5,-20(s0) +80000a1c: fac42783 lw a5,-84(s0) +80000a20: fef42423 sw a5,-24(s0) +80000a24: fd842783 lw a5,-40(s0) +80000a28: 00c7a783 lw a5,12(a5) +80000a2c: fcf42423 sw a5,-56(s0) +80000a30: fe042223 sw zero,-28(s0) +80000a34: 1240006f j 80000b58 <_vx_mat_mult+0x1ac> +80000a38: fe042023 sw zero,-32(s0) +80000a3c: fc042e23 sw zero,-36(s0) +80000a40: 0780006f j 80000ab8 <_vx_mat_mult+0x10c> +80000a44: fa842703 lw a4,-88(s0) +80000a48: fc842783 lw a5,-56(s0) +80000a4c: 02f707b3 mul a5,a4,a5 +80000a50: fdc42703 lw a4,-36(s0) +80000a54: 00f707b3 add a5,a4,a5 +80000a58: fcf42223 sw a5,-60(s0) +80000a5c: fc842703 lw a4,-56(s0) +80000a60: fdc42783 lw a5,-36(s0) +80000a64: 02f707b3 mul a5,a4,a5 +80000a68: fe842703 lw a4,-24(s0) +80000a6c: 00f707b3 add a5,a4,a5 +80000a70: fcf42023 sw a5,-64(s0) +80000a74: fc442783 lw a5,-60(s0) +80000a78: 00279793 slli a5,a5,0x2 +80000a7c: fd442703 lw a4,-44(s0) +80000a80: 00f707b3 add a5,a4,a5 +80000a84: 0007a703 lw a4,0(a5) +80000a88: fc042783 lw a5,-64(s0) +80000a8c: 00279793 slli a5,a5,0x2 +80000a90: fd042683 lw a3,-48(s0) +80000a94: 00f687b3 add a5,a3,a5 +80000a98: 0007a783 lw a5,0(a5) +80000a9c: 02f707b3 mul a5,a4,a5 +80000aa0: fe042703 lw a4,-32(s0) +80000aa4: 00f707b3 add a5,a4,a5 +80000aa8: fef42023 sw a5,-32(s0) +80000aac: fdc42783 lw a5,-36(s0) +80000ab0: 00178793 addi a5,a5,1 +80000ab4: fcf42e23 sw a5,-36(s0) +80000ab8: fdc42703 lw a4,-36(s0) +80000abc: fc842783 lw a5,-56(s0) +80000ac0: f8f762e3 bltu a4,a5,80000a44 <_vx_mat_mult+0x98> +80000ac4: fa842703 lw a4,-88(s0) +80000ac8: fc842783 lw a5,-56(s0) +80000acc: 02f70733 mul a4,a4,a5 +80000ad0: fe842783 lw a5,-24(s0) +80000ad4: 00f707b3 add a5,a4,a5 +80000ad8: faf42e23 sw a5,-68(s0) +80000adc: fe842703 lw a4,-24(s0) +80000ae0: fc842783 lw a5,-56(s0) +80000ae4: 00f737b3 sltu a5,a4,a5 +80000ae8: 0ff7f793 andi a5,a5,255 +80000aec: faf42c23 sw a5,-72(s0) +80000af0: fb842783 lw a5,-72(s0) +80000af4: 0017b793 seqz a5,a5 +80000af8: faf40ba3 sb a5,-73(s0) +80000afc: fb744783 lbu a5,-73(s0) +80000b00: 00078f13 mv t5,a5 +80000b04: 800017b7 lui a5,0x80001 +80000b08: b4478f93 addi t6,a5,-1212 # 80000b44 +80000b0c: 000f206b 0xf206b +80000b10: 01ff707b 0x1ff707b +80000b14: fbc42783 lw a5,-68(s0) +80000b18: 00279793 slli a5,a5,0x2 +80000b1c: fcc42703 lw a4,-52(s0) +80000b20: 00f707b3 add a5,a4,a5 +80000b24: fe042703 lw a4,-32(s0) +80000b28: 00e7a023 sw a4,0(a5) +80000b2c: fe842783 lw a5,-24(s0) +80000b30: 00178793 addi a5,a5,1 +80000b34: fef42423 sw a5,-24(s0) +80000b38: 800017b7 lui a5,0x80001 +80000b3c: b4878e13 addi t3,a5,-1208 # 80000b48 +80000b40: 000e0067 jr t3 +80000b44: 00000013 nop +80000b48: 0000306b 0x306b +80000b4c: fe442783 lw a5,-28(s0) +80000b50: 00178793 addi a5,a5,1 +80000b54: fef42223 sw a5,-28(s0) +80000b58: fe442783 lw a5,-28(s0) +80000b5c: fec42703 lw a4,-20(s0) +80000b60: ece7ece3 bltu a5,a4,80000a38 <_vx_mat_mult+0x8c> +80000b64: 00000013 nop +80000b68: 05c12083 lw ra,92(sp) +80000b6c: 05812403 lw s0,88(sp) +80000b70: 06010113 addi sp,sp,96 +80000b74: 00008067 ret + +80000b78 : +80000b78: fc010113 addi sp,sp,-64 +80000b7c: 02112e23 sw ra,60(sp) +80000b80: 02812c23 sw s0,56(sp) +80000b84: 04010413 addi s0,sp,64 +80000b88: fca42e23 sw a0,-36(s0) +80000b8c: fcb42c23 sw a1,-40(s0) +80000b90: fcc42a23 sw a2,-44(s0) +80000b94: fcd42823 sw a3,-48(s0) +80000b98: fce42623 sw a4,-52(s0) +80000b9c: 810037b7 lui a5,0x81003 +80000ba0: fdc42703 lw a4,-36(s0) +80000ba4: 9ae7ac23 sw a4,-1608(a5) # 810029b8 +80000ba8: 810037b7 lui a5,0x81003 +80000bac: 9b878793 addi a5,a5,-1608 # 810029b8 +80000bb0: fd842703 lw a4,-40(s0) +80000bb4: 00e7a223 sw a4,4(a5) +80000bb8: 810037b7 lui a5,0x81003 +80000bbc: 9b878793 addi a5,a5,-1608 # 810029b8 +80000bc0: fd442703 lw a4,-44(s0) +80000bc4: 00e7a423 sw a4,8(a5) +80000bc8: 810037b7 lui a5,0x81003 +80000bcc: 9b878793 addi a5,a5,-1608 # 810029b8 +80000bd0: fcc42703 lw a4,-52(s0) +80000bd4: 00e7a623 sw a4,12(a5) +80000bd8: 810037b7 lui a5,0x81003 +80000bdc: 9b878793 addi a5,a5,-1608 # 810029b8 +80000be0: fd042703 lw a4,-48(s0) +80000be4: 00e7a823 sw a4,16(a5) +80000be8: dc4ff0ef jal ra,800001ac +80000bec: fea42423 sw a0,-24(s0) +80000bf0: fcc42703 lw a4,-52(s0) +80000bf4: fe842783 lw a5,-24(s0) +80000bf8: 02f757b3 divu a5,a4,a5 +80000bfc: fef42623 sw a5,-20(s0) +80000c00: fcc42703 lw a4,-52(s0) +80000c04: fe842783 lw a5,-24(s0) +80000c08: 02f777b3 remu a5,a4,a5 +80000c0c: 00078863 beqz a5,80000c1c +80000c10: fec42783 lw a5,-20(s0) +80000c14: 00178793 addi a5,a5,1 +80000c18: fef42623 sw a5,-20(s0) +80000c1c: 810037b7 lui a5,0x81003 +80000c20: 9b878793 addi a5,a5,-1608 # 810029b8 +80000c24: fec42703 lw a4,-20(s0) +80000c28: 00e7aa23 sw a4,20(a5) +80000c2c: fcc42703 lw a4,-52(s0) +80000c30: fe842783 lw a5,-24(s0) +80000c34: 02f76263 bltu a4,a5,80000c58 +80000c38: 810037b7 lui a5,0x81003 +80000c3c: 9b878693 addi a3,a5,-1608 # 810029b8 +80000c40: 800017b7 lui a5,0x80001 +80000c44: cb078613 addi a2,a5,-848 # 80000cb0 +80000c48: fe842583 lw a1,-24(s0) +80000c4c: fd042503 lw a0,-48(s0) +80000c50: fbcff0ef jal ra,8000040c +80000c54: 0200006f j 80000c74 +80000c58: 810037b7 lui a5,0x81003 +80000c5c: 9b878693 addi a3,a5,-1608 # 810029b8 +80000c60: 800017b7 lui a5,0x80001 +80000c64: cb078613 addi a2,a5,-848 # 80000cb0 +80000c68: fcc42583 lw a1,-52(s0) +80000c6c: fd042503 lw a0,-48(s0) +80000c70: f9cff0ef jal ra,8000040c +80000c74: d30ff0ef jal ra,800001a4 +80000c78: fea42223 sw a0,-28(s0) +80000c7c: fd042703 lw a4,-48(s0) +80000c80: fe442783 lw a5,-28(s0) +80000c84: 00e7f863 bgeu a5,a4,80000c94 +80000c88: fe442503 lw a0,-28(s0) +80000c8c: 86dff0ef jal ra,800004f8 +80000c90: 00c0006f j 80000c9c +80000c94: fd042503 lw a0,-48(s0) +80000c98: 861ff0ef jal ra,800004f8 +80000c9c: 00000013 nop +80000ca0: 03c12083 lw ra,60(sp) +80000ca4: 03812403 lw s0,56(sp) +80000ca8: 04010113 addi sp,sp,64 +80000cac: 00008067 ret + +80000cb0 <_vx_mat_add>: +80000cb0: fb010113 addi sp,sp,-80 +80000cb4: 04112623 sw ra,76(sp) +80000cb8: 04812423 sw s0,72(sp) +80000cbc: 05010413 addi s0,sp,80 +80000cc0: faa42e23 sw a0,-68(s0) +80000cc4: fab42c23 sw a1,-72(s0) +80000cc8: 8fdff0ef jal ra,800005c4 +80000ccc: fea42023 sw a0,-32(s0) +80000cd0: fe042783 lw a5,-32(s0) +80000cd4: 0007a783 lw a5,0(a5) +80000cd8: fcf42e23 sw a5,-36(s0) +80000cdc: fe042783 lw a5,-32(s0) +80000ce0: 0047a783 lw a5,4(a5) +80000ce4: fcf42c23 sw a5,-40(s0) +80000ce8: fe042783 lw a5,-32(s0) +80000cec: 0087a783 lw a5,8(a5) +80000cf0: fcf42a23 sw a5,-44(s0) +80000cf4: fe042783 lw a5,-32(s0) +80000cf8: 0147a783 lw a5,20(a5) +80000cfc: fef42623 sw a5,-20(s0) +80000d00: fec42703 lw a4,-20(s0) +80000d04: fbc42783 lw a5,-68(s0) +80000d08: 02f707b3 mul a5,a4,a5 +80000d0c: fef42423 sw a5,-24(s0) +80000d10: fec42783 lw a5,-20(s0) +80000d14: 00079a63 bnez a5,80000d28 <_vx_mat_add+0x78> +80000d18: 00100793 li a5,1 +80000d1c: fef42623 sw a5,-20(s0) +80000d20: fbc42783 lw a5,-68(s0) +80000d24: fef42423 sw a5,-24(s0) +80000d28: fe042783 lw a5,-32(s0) +80000d2c: 00c7a783 lw a5,12(a5) +80000d30: fcf42823 sw a5,-48(s0) +80000d34: fe042223 sw zero,-28(s0) +80000d38: 0c00006f j 80000df8 <_vx_mat_add+0x148> +80000d3c: fb842703 lw a4,-72(s0) +80000d40: fd042783 lw a5,-48(s0) +80000d44: 02f70733 mul a4,a4,a5 +80000d48: fe842783 lw a5,-24(s0) +80000d4c: 00f707b3 add a5,a4,a5 +80000d50: fcf42623 sw a5,-52(s0) +80000d54: fe842703 lw a4,-24(s0) +80000d58: fd042783 lw a5,-48(s0) +80000d5c: 00f737b3 sltu a5,a4,a5 +80000d60: 0ff7f793 andi a5,a5,255 +80000d64: fcf42423 sw a5,-56(s0) +80000d68: fc842783 lw a5,-56(s0) +80000d6c: 0017b793 seqz a5,a5 +80000d70: fcf403a3 sb a5,-57(s0) +80000d74: fc744783 lbu a5,-57(s0) +80000d78: 00078f13 mv t5,a5 +80000d7c: 800017b7 lui a5,0x80001 +80000d80: de478f93 addi t6,a5,-540 # 80000de4 +80000d84: 000f206b 0xf206b +80000d88: 01ff707b 0x1ff707b +80000d8c: fcc42783 lw a5,-52(s0) +80000d90: 00279793 slli a5,a5,0x2 +80000d94: fdc42703 lw a4,-36(s0) +80000d98: 00f707b3 add a5,a4,a5 +80000d9c: 0007a683 lw a3,0(a5) +80000da0: fcc42783 lw a5,-52(s0) +80000da4: 00279793 slli a5,a5,0x2 +80000da8: fd842703 lw a4,-40(s0) +80000dac: 00f707b3 add a5,a4,a5 +80000db0: 0007a703 lw a4,0(a5) +80000db4: fcc42783 lw a5,-52(s0) +80000db8: 00279793 slli a5,a5,0x2 +80000dbc: fd442603 lw a2,-44(s0) +80000dc0: 00f607b3 add a5,a2,a5 +80000dc4: 00e68733 add a4,a3,a4 +80000dc8: 00e7a023 sw a4,0(a5) +80000dcc: fe842783 lw a5,-24(s0) +80000dd0: 00178793 addi a5,a5,1 +80000dd4: fef42423 sw a5,-24(s0) +80000dd8: 800017b7 lui a5,0x80001 +80000ddc: de878e13 addi t3,a5,-536 # 80000de8 +80000de0: 000e0067 jr t3 +80000de4: 00000013 nop +80000de8: 0000306b 0x306b +80000dec: fe442783 lw a5,-28(s0) +80000df0: 00178793 addi a5,a5,1 +80000df4: fef42223 sw a5,-28(s0) +80000df8: fe442783 lw a5,-28(s0) +80000dfc: fec42703 lw a4,-20(s0) +80000e00: f2e7eee3 bltu a5,a4,80000d3c <_vx_mat_add+0x8c> +80000e04: 00000013 nop +80000e08: 04c12083 lw ra,76(sp) +80000e0c: 04812403 lw s0,72(sp) +80000e10: 05010113 addi sp,sp,80 +80000e14: 00008067 ret + +80000e18 : +80000e18: fc010113 addi sp,sp,-64 +80000e1c: 02112e23 sw ra,60(sp) +80000e20: 02812c23 sw s0,56(sp) +80000e24: 04010413 addi s0,sp,64 +80000e28: fca42e23 sw a0,-36(s0) +80000e2c: fcb42c23 sw a1,-40(s0) +80000e30: fcc42a23 sw a2,-44(s0) +80000e34: fcd42823 sw a3,-48(s0) +80000e38: fce42623 sw a4,-52(s0) +80000e3c: 810037b7 lui a5,0x81003 +80000e40: fdc42703 lw a4,-36(s0) +80000e44: 9ae7ac23 sw a4,-1608(a5) # 810029b8 +80000e48: 810037b7 lui a5,0x81003 +80000e4c: 9b878793 addi a5,a5,-1608 # 810029b8 +80000e50: fd842703 lw a4,-40(s0) +80000e54: 00e7a223 sw a4,4(a5) +80000e58: 810037b7 lui a5,0x81003 +80000e5c: 9b878793 addi a5,a5,-1608 # 810029b8 +80000e60: fd442703 lw a4,-44(s0) +80000e64: 00e7a423 sw a4,8(a5) +80000e68: 810037b7 lui a5,0x81003 +80000e6c: 9b878793 addi a5,a5,-1608 # 810029b8 +80000e70: fcc42703 lw a4,-52(s0) +80000e74: 00e7a623 sw a4,12(a5) +80000e78: 810037b7 lui a5,0x81003 +80000e7c: 9b878793 addi a5,a5,-1608 # 810029b8 +80000e80: fd042703 lw a4,-48(s0) +80000e84: 00e7a823 sw a4,16(a5) +80000e88: b24ff0ef jal ra,800001ac +80000e8c: fea42423 sw a0,-24(s0) +80000e90: fcc42703 lw a4,-52(s0) +80000e94: fe842783 lw a5,-24(s0) +80000e98: 02f757b3 divu a5,a4,a5 +80000e9c: fef42623 sw a5,-20(s0) +80000ea0: fcc42703 lw a4,-52(s0) +80000ea4: fe842783 lw a5,-24(s0) +80000ea8: 02f777b3 remu a5,a4,a5 +80000eac: 00078863 beqz a5,80000ebc +80000eb0: fec42783 lw a5,-20(s0) +80000eb4: 00178793 addi a5,a5,1 +80000eb8: fef42623 sw a5,-20(s0) +80000ebc: 810037b7 lui a5,0x81003 +80000ec0: 9b878793 addi a5,a5,-1608 # 810029b8 +80000ec4: fec42703 lw a4,-20(s0) +80000ec8: 00e7aa23 sw a4,20(a5) +80000ecc: fcc42703 lw a4,-52(s0) +80000ed0: fe842783 lw a5,-24(s0) +80000ed4: 02f76263 bltu a4,a5,80000ef8 +80000ed8: 810037b7 lui a5,0x81003 +80000edc: 9b878693 addi a3,a5,-1608 # 810029b8 +80000ee0: 800017b7 lui a5,0x80001 +80000ee4: f5078613 addi a2,a5,-176 # 80000f50 +80000ee8: fe842583 lw a1,-24(s0) +80000eec: fd042503 lw a0,-48(s0) +80000ef0: d1cff0ef jal ra,8000040c +80000ef4: 0200006f j 80000f14 +80000ef8: 810037b7 lui a5,0x81003 +80000efc: 9b878693 addi a3,a5,-1608 # 810029b8 +80000f00: 800017b7 lui a5,0x80001 +80000f04: f5078613 addi a2,a5,-176 # 80000f50 +80000f08: fcc42583 lw a1,-52(s0) +80000f0c: fd042503 lw a0,-48(s0) +80000f10: cfcff0ef jal ra,8000040c +80000f14: a90ff0ef jal ra,800001a4 +80000f18: fea42223 sw a0,-28(s0) +80000f1c: fd042703 lw a4,-48(s0) +80000f20: fe442783 lw a5,-28(s0) +80000f24: 00e7f863 bgeu a5,a4,80000f34 +80000f28: fe442503 lw a0,-28(s0) +80000f2c: dccff0ef jal ra,800004f8 +80000f30: 00c0006f j 80000f3c +80000f34: fd042503 lw a0,-48(s0) +80000f38: dc0ff0ef jal ra,800004f8 +80000f3c: 00000013 nop +80000f40: 03c12083 lw ra,60(sp) +80000f44: 03812403 lw s0,56(sp) +80000f48: 04010113 addi sp,sp,64 +80000f4c: 00008067 ret + +80000f50 <_vx_mat_sub>: +80000f50: fb010113 addi sp,sp,-80 +80000f54: 04112623 sw ra,76(sp) +80000f58: 04812423 sw s0,72(sp) +80000f5c: 05010413 addi s0,sp,80 +80000f60: faa42e23 sw a0,-68(s0) +80000f64: fab42c23 sw a1,-72(s0) +80000f68: e5cff0ef jal ra,800005c4 +80000f6c: fea42023 sw a0,-32(s0) +80000f70: fe042783 lw a5,-32(s0) +80000f74: 0007a783 lw a5,0(a5) +80000f78: fcf42e23 sw a5,-36(s0) +80000f7c: fe042783 lw a5,-32(s0) +80000f80: 0047a783 lw a5,4(a5) +80000f84: fcf42c23 sw a5,-40(s0) +80000f88: fe042783 lw a5,-32(s0) +80000f8c: 0087a783 lw a5,8(a5) +80000f90: fcf42a23 sw a5,-44(s0) +80000f94: fe042783 lw a5,-32(s0) +80000f98: 0147a783 lw a5,20(a5) +80000f9c: fef42623 sw a5,-20(s0) +80000fa0: fec42703 lw a4,-20(s0) +80000fa4: fbc42783 lw a5,-68(s0) +80000fa8: 02f707b3 mul a5,a4,a5 +80000fac: fef42423 sw a5,-24(s0) +80000fb0: fec42783 lw a5,-20(s0) +80000fb4: 00079a63 bnez a5,80000fc8 <_vx_mat_sub+0x78> +80000fb8: 00100793 li a5,1 +80000fbc: fef42623 sw a5,-20(s0) +80000fc0: fbc42783 lw a5,-68(s0) +80000fc4: fef42423 sw a5,-24(s0) +80000fc8: fe042783 lw a5,-32(s0) +80000fcc: 00c7a783 lw a5,12(a5) +80000fd0: fcf42823 sw a5,-48(s0) +80000fd4: fe042223 sw zero,-28(s0) +80000fd8: 0c00006f j 80001098 <_vx_mat_sub+0x148> +80000fdc: fb842703 lw a4,-72(s0) +80000fe0: fd042783 lw a5,-48(s0) +80000fe4: 02f70733 mul a4,a4,a5 +80000fe8: fe842783 lw a5,-24(s0) +80000fec: 00f707b3 add a5,a4,a5 +80000ff0: fcf42623 sw a5,-52(s0) +80000ff4: fe842703 lw a4,-24(s0) +80000ff8: fd042783 lw a5,-48(s0) +80000ffc: 00f737b3 sltu a5,a4,a5 +80001000: 0ff7f793 andi a5,a5,255 +80001004: fcf42423 sw a5,-56(s0) +80001008: fc842783 lw a5,-56(s0) +8000100c: 0017b793 seqz a5,a5 +80001010: fcf403a3 sb a5,-57(s0) +80001014: fc744783 lbu a5,-57(s0) +80001018: 00078f13 mv t5,a5 +8000101c: 800017b7 lui a5,0x80001 +80001020: 08478f93 addi t6,a5,132 # 80001084 +80001024: 000f206b 0xf206b +80001028: 01ff707b 0x1ff707b +8000102c: fcc42783 lw a5,-52(s0) +80001030: 00279793 slli a5,a5,0x2 +80001034: fdc42703 lw a4,-36(s0) +80001038: 00f707b3 add a5,a4,a5 +8000103c: 0007a683 lw a3,0(a5) +80001040: fcc42783 lw a5,-52(s0) +80001044: 00279793 slli a5,a5,0x2 +80001048: fd842703 lw a4,-40(s0) +8000104c: 00f707b3 add a5,a4,a5 +80001050: 0007a703 lw a4,0(a5) +80001054: fcc42783 lw a5,-52(s0) +80001058: 00279793 slli a5,a5,0x2 +8000105c: fd442603 lw a2,-44(s0) +80001060: 00f607b3 add a5,a2,a5 +80001064: 40e68733 sub a4,a3,a4 +80001068: 00e7a023 sw a4,0(a5) +8000106c: fe842783 lw a5,-24(s0) +80001070: 00178793 addi a5,a5,1 +80001074: fef42423 sw a5,-24(s0) +80001078: 800017b7 lui a5,0x80001 +8000107c: 08878e13 addi t3,a5,136 # 80001088 +80001080: 000e0067 jr t3 +80001084: 00000013 nop +80001088: 0000306b 0x306b +8000108c: fe442783 lw a5,-28(s0) +80001090: 00178793 addi a5,a5,1 +80001094: fef42223 sw a5,-28(s0) +80001098: fe442783 lw a5,-28(s0) +8000109c: fec42703 lw a4,-20(s0) +800010a0: f2e7eee3 bltu a5,a4,80000fdc <_vx_mat_sub+0x8c> +800010a4: 00000013 nop +800010a8: 04c12083 lw ra,76(sp) +800010ac: 04812403 lw s0,72(sp) +800010b0: 05010113 addi sp,sp,80 +800010b4: 00008067 ret + +800010b8 : +800010b8: fc010113 addi sp,sp,-64 +800010bc: 02112e23 sw ra,60(sp) +800010c0: 02812c23 sw s0,56(sp) +800010c4: 04010413 addi s0,sp,64 +800010c8: fca42e23 sw a0,-36(s0) +800010cc: fcb42c23 sw a1,-40(s0) +800010d0: fcc42a23 sw a2,-44(s0) +800010d4: fcd42823 sw a3,-48(s0) +800010d8: fce42623 sw a4,-52(s0) +800010dc: 810037b7 lui a5,0x81003 +800010e0: fdc42703 lw a4,-36(s0) +800010e4: 9ce7a823 sw a4,-1584(a5) # 810029d0 +800010e8: 810037b7 lui a5,0x81003 +800010ec: 9d078793 addi a5,a5,-1584 # 810029d0 +800010f0: fd842703 lw a4,-40(s0) +800010f4: 00e7a223 sw a4,4(a5) +800010f8: 810037b7 lui a5,0x81003 +800010fc: 9d078793 addi a5,a5,-1584 # 810029d0 +80001100: fd442703 lw a4,-44(s0) +80001104: 00e7a423 sw a4,8(a5) +80001108: 810037b7 lui a5,0x81003 +8000110c: 9d078793 addi a5,a5,-1584 # 810029d0 +80001110: fcc42703 lw a4,-52(s0) +80001114: 00e7a623 sw a4,12(a5) +80001118: 810037b7 lui a5,0x81003 +8000111c: 9d078793 addi a5,a5,-1584 # 810029d0 +80001120: fd042703 lw a4,-48(s0) +80001124: 00e7a823 sw a4,16(a5) +80001128: 884ff0ef jal ra,800001ac +8000112c: fea42423 sw a0,-24(s0) +80001130: fcc42703 lw a4,-52(s0) +80001134: fe842783 lw a5,-24(s0) +80001138: 02f757b3 divu a5,a4,a5 +8000113c: fef42623 sw a5,-20(s0) +80001140: fcc42703 lw a4,-52(s0) +80001144: fe842783 lw a5,-24(s0) +80001148: 02f777b3 remu a5,a4,a5 +8000114c: 00078863 beqz a5,8000115c +80001150: fec42783 lw a5,-20(s0) +80001154: 00178793 addi a5,a5,1 +80001158: fef42623 sw a5,-20(s0) +8000115c: 810037b7 lui a5,0x81003 +80001160: 9d078793 addi a5,a5,-1584 # 810029d0 +80001164: fec42703 lw a4,-20(s0) +80001168: 00e7aa23 sw a4,20(a5) +8000116c: fcc42703 lw a4,-52(s0) +80001170: fe842783 lw a5,-24(s0) +80001174: 02f76263 bltu a4,a5,80001198 +80001178: 810037b7 lui a5,0x81003 +8000117c: 9d078693 addi a3,a5,-1584 # 810029d0 +80001180: 800017b7 lui a5,0x80001 +80001184: 1f078613 addi a2,a5,496 # 800011f0 +80001188: fe842583 lw a1,-24(s0) +8000118c: fd042503 lw a0,-48(s0) +80001190: a7cff0ef jal ra,8000040c +80001194: 0200006f j 800011b4 +80001198: 810037b7 lui a5,0x81003 +8000119c: 9d078693 addi a3,a5,-1584 # 810029d0 +800011a0: 800017b7 lui a5,0x80001 +800011a4: 1f078613 addi a2,a5,496 # 800011f0 +800011a8: fcc42583 lw a1,-52(s0) +800011ac: fd042503 lw a0,-48(s0) +800011b0: a5cff0ef jal ra,8000040c +800011b4: ff1fe0ef jal ra,800001a4 +800011b8: fea42223 sw a0,-28(s0) +800011bc: fd042703 lw a4,-48(s0) +800011c0: fe442783 lw a5,-28(s0) +800011c4: 00e7f863 bgeu a5,a4,800011d4 +800011c8: fe442503 lw a0,-28(s0) +800011cc: b2cff0ef jal ra,800004f8 +800011d0: 00c0006f j 800011dc +800011d4: fd042503 lw a0,-48(s0) +800011d8: b20ff0ef jal ra,800004f8 +800011dc: 00000013 nop +800011e0: 03c12083 lw ra,60(sp) +800011e4: 03812403 lw s0,56(sp) +800011e8: 04010113 addi sp,sp,64 +800011ec: 00008067 ret + +800011f0 <_vx_e_mat_add>: +800011f0: fb010113 addi sp,sp,-80 +800011f4: 04112623 sw ra,76(sp) +800011f8: 04812423 sw s0,72(sp) +800011fc: 05010413 addi s0,sp,80 +80001200: faa42e23 sw a0,-68(s0) +80001204: fab42c23 sw a1,-72(s0) +80001208: bbcff0ef jal ra,800005c4 +8000120c: fea42023 sw a0,-32(s0) +80001210: fe042783 lw a5,-32(s0) +80001214: 0007a783 lw a5,0(a5) +80001218: fcf42e23 sw a5,-36(s0) +8000121c: fe042783 lw a5,-32(s0) +80001220: 0047a783 lw a5,4(a5) +80001224: 0007a783 lw a5,0(a5) +80001228: fcf42c23 sw a5,-40(s0) +8000122c: fe042783 lw a5,-32(s0) +80001230: 0087a783 lw a5,8(a5) +80001234: fcf42a23 sw a5,-44(s0) +80001238: fe042783 lw a5,-32(s0) +8000123c: 0147a783 lw a5,20(a5) +80001240: fef42623 sw a5,-20(s0) +80001244: fec42703 lw a4,-20(s0) +80001248: fbc42783 lw a5,-68(s0) +8000124c: 02f707b3 mul a5,a4,a5 +80001250: fef42423 sw a5,-24(s0) +80001254: fec42783 lw a5,-20(s0) +80001258: 00079a63 bnez a5,8000126c <_vx_e_mat_add+0x7c> +8000125c: 00100793 li a5,1 +80001260: fef42623 sw a5,-20(s0) +80001264: fbc42783 lw a5,-68(s0) +80001268: fef42423 sw a5,-24(s0) +8000126c: fe042783 lw a5,-32(s0) +80001270: 00c7a783 lw a5,12(a5) +80001274: fcf42823 sw a5,-48(s0) +80001278: fe042223 sw zero,-28(s0) +8000127c: 0b00006f j 8000132c <_vx_e_mat_add+0x13c> +80001280: fb842703 lw a4,-72(s0) +80001284: fd042783 lw a5,-48(s0) +80001288: 02f70733 mul a4,a4,a5 +8000128c: fe842783 lw a5,-24(s0) +80001290: 00f707b3 add a5,a4,a5 +80001294: fcf42623 sw a5,-52(s0) +80001298: fe842703 lw a4,-24(s0) +8000129c: fd042783 lw a5,-48(s0) +800012a0: 00f737b3 sltu a5,a4,a5 +800012a4: 0ff7f793 andi a5,a5,255 +800012a8: fcf42423 sw a5,-56(s0) +800012ac: fc842783 lw a5,-56(s0) +800012b0: 0017b793 seqz a5,a5 +800012b4: fcf403a3 sb a5,-57(s0) +800012b8: fc744783 lbu a5,-57(s0) +800012bc: 00078f13 mv t5,a5 +800012c0: 800017b7 lui a5,0x80001 +800012c4: 31878f93 addi t6,a5,792 # 80001318 +800012c8: 000f206b 0xf206b +800012cc: 01ff707b 0x1ff707b +800012d0: fcc42783 lw a5,-52(s0) +800012d4: 00279793 slli a5,a5,0x2 +800012d8: fdc42703 lw a4,-36(s0) +800012dc: 00f707b3 add a5,a4,a5 +800012e0: 0007a683 lw a3,0(a5) +800012e4: fcc42783 lw a5,-52(s0) +800012e8: 00279793 slli a5,a5,0x2 +800012ec: fd442703 lw a4,-44(s0) +800012f0: 00f707b3 add a5,a4,a5 +800012f4: fd842703 lw a4,-40(s0) +800012f8: 00e68733 add a4,a3,a4 +800012fc: 00e7a023 sw a4,0(a5) +80001300: fe842783 lw a5,-24(s0) +80001304: 00178793 addi a5,a5,1 +80001308: fef42423 sw a5,-24(s0) +8000130c: 800017b7 lui a5,0x80001 +80001310: 31c78e13 addi t3,a5,796 # 8000131c +80001314: 000e0067 jr t3 +80001318: 00000013 nop +8000131c: 0000306b 0x306b +80001320: fe442783 lw a5,-28(s0) +80001324: 00178793 addi a5,a5,1 +80001328: fef42223 sw a5,-28(s0) +8000132c: fe442783 lw a5,-28(s0) +80001330: fec42703 lw a4,-20(s0) +80001334: f4e7e6e3 bltu a5,a4,80001280 <_vx_e_mat_add+0x90> +80001338: 00000013 nop +8000133c: 04c12083 lw ra,76(sp) +80001340: 04812403 lw s0,72(sp) +80001344: 05010113 addi sp,sp,80 +80001348: 00008067 ret + +8000134c : +8000134c: fc010113 addi sp,sp,-64 +80001350: 02112e23 sw ra,60(sp) +80001354: 02812c23 sw s0,56(sp) +80001358: 04010413 addi s0,sp,64 +8000135c: fca42e23 sw a0,-36(s0) +80001360: fcb42c23 sw a1,-40(s0) +80001364: fcc42a23 sw a2,-44(s0) +80001368: fcd42823 sw a3,-48(s0) +8000136c: fce42623 sw a4,-52(s0) +80001370: 810037b7 lui a5,0x81003 +80001374: fdc42703 lw a4,-36(s0) +80001378: 9ce7a823 sw a4,-1584(a5) # 810029d0 +8000137c: 810037b7 lui a5,0x81003 +80001380: 9d078793 addi a5,a5,-1584 # 810029d0 +80001384: fd842703 lw a4,-40(s0) +80001388: 00e7a223 sw a4,4(a5) +8000138c: 810037b7 lui a5,0x81003 +80001390: 9d078793 addi a5,a5,-1584 # 810029d0 +80001394: fd442703 lw a4,-44(s0) +80001398: 00e7a423 sw a4,8(a5) +8000139c: 810037b7 lui a5,0x81003 +800013a0: 9d078793 addi a5,a5,-1584 # 810029d0 +800013a4: fcc42703 lw a4,-52(s0) +800013a8: 00e7a623 sw a4,12(a5) +800013ac: 810037b7 lui a5,0x81003 +800013b0: 9d078793 addi a5,a5,-1584 # 810029d0 +800013b4: fd042703 lw a4,-48(s0) +800013b8: 00e7a823 sw a4,16(a5) +800013bc: df1fe0ef jal ra,800001ac +800013c0: fea42423 sw a0,-24(s0) +800013c4: fcc42703 lw a4,-52(s0) +800013c8: fe842783 lw a5,-24(s0) +800013cc: 02f757b3 divu a5,a4,a5 +800013d0: fef42623 sw a5,-20(s0) +800013d4: fcc42703 lw a4,-52(s0) +800013d8: fe842783 lw a5,-24(s0) +800013dc: 02f777b3 remu a5,a4,a5 +800013e0: 00078863 beqz a5,800013f0 +800013e4: fec42783 lw a5,-20(s0) +800013e8: 00178793 addi a5,a5,1 +800013ec: fef42623 sw a5,-20(s0) +800013f0: 810037b7 lui a5,0x81003 +800013f4: 9d078793 addi a5,a5,-1584 # 810029d0 +800013f8: fec42703 lw a4,-20(s0) +800013fc: 00e7aa23 sw a4,20(a5) +80001400: fcc42703 lw a4,-52(s0) +80001404: fe842783 lw a5,-24(s0) +80001408: 02f76263 bltu a4,a5,8000142c +8000140c: 810037b7 lui a5,0x81003 +80001410: 9d078693 addi a3,a5,-1584 # 810029d0 +80001414: 800017b7 lui a5,0x80001 +80001418: 48478613 addi a2,a5,1156 # 80001484 +8000141c: fe842583 lw a1,-24(s0) +80001420: fd042503 lw a0,-48(s0) +80001424: fe9fe0ef jal ra,8000040c +80001428: 0200006f j 80001448 +8000142c: 810037b7 lui a5,0x81003 +80001430: 9d078693 addi a3,a5,-1584 # 810029d0 +80001434: 800017b7 lui a5,0x80001 +80001438: 48478613 addi a2,a5,1156 # 80001484 +8000143c: fcc42583 lw a1,-52(s0) +80001440: fd042503 lw a0,-48(s0) +80001444: fc9fe0ef jal ra,8000040c +80001448: d5dfe0ef jal ra,800001a4 +8000144c: fea42223 sw a0,-28(s0) +80001450: fd042703 lw a4,-48(s0) +80001454: fe442783 lw a5,-28(s0) +80001458: 00e7f863 bgeu a5,a4,80001468 +8000145c: fe442503 lw a0,-28(s0) +80001460: 898ff0ef jal ra,800004f8 +80001464: 00c0006f j 80001470 +80001468: fd042503 lw a0,-48(s0) +8000146c: 88cff0ef jal ra,800004f8 +80001470: 00000013 nop +80001474: 03c12083 lw ra,60(sp) +80001478: 03812403 lw s0,56(sp) +8000147c: 04010113 addi sp,sp,64 +80001480: 00008067 ret + +80001484 <_vx_e_mat_mult>: +80001484: fb010113 addi sp,sp,-80 +80001488: 04112623 sw ra,76(sp) +8000148c: 04812423 sw s0,72(sp) +80001490: 05010413 addi s0,sp,80 +80001494: faa42e23 sw a0,-68(s0) +80001498: fab42c23 sw a1,-72(s0) +8000149c: 928ff0ef jal ra,800005c4 +800014a0: fea42023 sw a0,-32(s0) +800014a4: fe042783 lw a5,-32(s0) +800014a8: 0007a783 lw a5,0(a5) +800014ac: fcf42e23 sw a5,-36(s0) +800014b0: fe042783 lw a5,-32(s0) +800014b4: 0047a783 lw a5,4(a5) +800014b8: 0007a783 lw a5,0(a5) +800014bc: fcf42c23 sw a5,-40(s0) +800014c0: fe042783 lw a5,-32(s0) +800014c4: 0087a783 lw a5,8(a5) +800014c8: fcf42a23 sw a5,-44(s0) +800014cc: fe042783 lw a5,-32(s0) +800014d0: 0147a783 lw a5,20(a5) +800014d4: fef42623 sw a5,-20(s0) +800014d8: fec42703 lw a4,-20(s0) +800014dc: fbc42783 lw a5,-68(s0) +800014e0: 02f707b3 mul a5,a4,a5 +800014e4: fef42423 sw a5,-24(s0) +800014e8: fec42783 lw a5,-20(s0) +800014ec: 00079a63 bnez a5,80001500 <_vx_e_mat_mult+0x7c> +800014f0: 00100793 li a5,1 +800014f4: fef42623 sw a5,-20(s0) +800014f8: fbc42783 lw a5,-68(s0) +800014fc: fef42423 sw a5,-24(s0) +80001500: fe042783 lw a5,-32(s0) +80001504: 00c7a783 lw a5,12(a5) +80001508: fcf42823 sw a5,-48(s0) +8000150c: fe042223 sw zero,-28(s0) +80001510: 0b00006f j 800015c0 <_vx_e_mat_mult+0x13c> +80001514: fb842703 lw a4,-72(s0) +80001518: fd042783 lw a5,-48(s0) +8000151c: 02f70733 mul a4,a4,a5 +80001520: fe842783 lw a5,-24(s0) +80001524: 00f707b3 add a5,a4,a5 +80001528: fcf42623 sw a5,-52(s0) +8000152c: fe842703 lw a4,-24(s0) +80001530: fd042783 lw a5,-48(s0) +80001534: 00f737b3 sltu a5,a4,a5 +80001538: 0ff7f793 andi a5,a5,255 +8000153c: fcf42423 sw a5,-56(s0) +80001540: fc842783 lw a5,-56(s0) +80001544: 0017b793 seqz a5,a5 +80001548: fcf403a3 sb a5,-57(s0) +8000154c: fc744783 lbu a5,-57(s0) +80001550: 00078f13 mv t5,a5 +80001554: 800017b7 lui a5,0x80001 +80001558: 5ac78f93 addi t6,a5,1452 # 800015ac +8000155c: 000f206b 0xf206b +80001560: 01ff707b 0x1ff707b +80001564: fcc42783 lw a5,-52(s0) +80001568: 00279793 slli a5,a5,0x2 +8000156c: fdc42703 lw a4,-36(s0) +80001570: 00f707b3 add a5,a4,a5 +80001574: 0007a683 lw a3,0(a5) +80001578: fcc42783 lw a5,-52(s0) +8000157c: 00279793 slli a5,a5,0x2 +80001580: fd442703 lw a4,-44(s0) +80001584: 00f707b3 add a5,a4,a5 +80001588: fd842703 lw a4,-40(s0) +8000158c: 02e68733 mul a4,a3,a4 +80001590: 00e7a023 sw a4,0(a5) +80001594: fe842783 lw a5,-24(s0) +80001598: 00178793 addi a5,a5,1 +8000159c: fef42423 sw a5,-24(s0) +800015a0: 800017b7 lui a5,0x80001 +800015a4: 5b078e13 addi t3,a5,1456 # 800015b0 +800015a8: 000e0067 jr t3 +800015ac: 00000013 nop +800015b0: 0000306b 0x306b +800015b4: fe442783 lw a5,-28(s0) +800015b8: 00178793 addi a5,a5,1 +800015bc: fef42223 sw a5,-28(s0) +800015c0: fe442783 lw a5,-28(s0) +800015c4: fec42703 lw a4,-20(s0) +800015c8: f4e7e6e3 bltu a5,a4,80001514 <_vx_e_mat_mult+0x90> +800015cc: 00000013 nop +800015d0: 04c12083 lw ra,76(sp) +800015d4: 04812403 lw s0,72(sp) +800015d8: 05010113 addi sp,sp,80 +800015dc: 00008067 ret + +800015e0 : +800015e0: fe010113 addi sp,sp,-32 +800015e4: 00812e23 sw s0,28(sp) +800015e8: 02010413 addi s0,sp,32 +800015ec: fe042623 sw zero,-20(s0) +800015f0: 0480006f j 80001638 +800015f4: 810037b7 lui a5,0x81003 +800015f8: fec42703 lw a4,-20(s0) +800015fc: 00271713 slli a4,a4,0x2 +80001600: 9e878793 addi a5,a5,-1560 # 810029e8 +80001604: 00f707b3 add a5,a4,a5 +80001608: 00300713 li a4,3 +8000160c: 00e7a023 sw a4,0(a5) +80001610: 810047b7 lui a5,0x81004 +80001614: fec42703 lw a4,-20(s0) +80001618: 00271713 slli a4,a4,0x2 +8000161c: 9e878793 addi a5,a5,-1560 # 810039e8 +80001620: 00f707b3 add a5,a4,a5 +80001624: 00200713 li a4,2 +80001628: 00e7a023 sw a4,0(a5) +8000162c: fec42783 lw a5,-20(s0) +80001630: 00178793 addi a5,a5,1 +80001634: fef42623 sw a5,-20(s0) +80001638: fec42703 lw a4,-20(s0) +8000163c: 0ff00793 li a5,255 +80001640: fae7dae3 bge a5,a4,800015f4 +80001644: 00000013 nop +80001648: 01c12403 lw s0,28(sp) +8000164c: 02010113 addi sp,sp,32 +80001650: 00008067 ret + +80001654 : +80001654: fd010113 addi sp,sp,-48 +80001658: 02112623 sw ra,44(sp) +8000165c: 02812423 sw s0,40(sp) +80001660: 03010413 addi s0,sp,48 +80001664: fca42e23 sw a0,-36(s0) +80001668: 810007b7 lui a5,0x81000 +8000166c: 11078513 addi a0,a5,272 # 81000110 +80001670: 8c0ff0ef jal ra,80000730 +80001674: fe042623 sw zero,-20(s0) +80001678: 0580006f j 800016d0 +8000167c: fec42783 lw a5,-20(s0) +80001680: 00078e63 beqz a5,8000169c +80001684: fec42783 lw a5,-20(s0) +80001688: 00f7f793 andi a5,a5,15 +8000168c: 00079863 bnez a5,8000169c +80001690: 810007b7 lui a5,0x81000 +80001694: 13478513 addi a0,a5,308 # 81000134 +80001698: 898ff0ef jal ra,80000730 +8000169c: fec42783 lw a5,-20(s0) +800016a0: 00279793 slli a5,a5,0x2 +800016a4: fdc42703 lw a4,-36(s0) +800016a8: 00f707b3 add a5,a4,a5 +800016ac: 0007a783 lw a5,0(a5) +800016b0: 00078513 mv a0,a5 +800016b4: 8b8ff0ef jal ra,8000076c +800016b8: 810007b7 lui a5,0x81000 +800016bc: 13878513 addi a0,a5,312 # 81000138 +800016c0: 870ff0ef jal ra,80000730 +800016c4: fec42783 lw a5,-20(s0) +800016c8: 00178793 addi a5,a5,1 +800016cc: fef42623 sw a5,-20(s0) +800016d0: fec42703 lw a4,-20(s0) +800016d4: 0ff00793 li a5,255 +800016d8: fae7d2e3 bge a5,a4,8000167c +800016dc: 810007b7 lui a5,0x81000 +800016e0: 13c78513 addi a0,a5,316 # 8100013c +800016e4: 84cff0ef jal ra,80000730 +800016e8: 00000013 nop +800016ec: 02c12083 lw ra,44(sp) +800016f0: 02812403 lw s0,40(sp) +800016f4: 03010113 addi sp,sp,48 +800016f8: 00008067 ret + +800016fc
: +800016fc: fe010113 addi sp,sp,-32 +80001700: 00112e23 sw ra,28(sp) +80001704: 00812c23 sw s0,24(sp) +80001708: 02010413 addi s0,sp,32 +8000170c: ed5ff0ef jal ra,800015e0 +80001710: 01000693 li a3,16 +80001714: 810057b7 lui a5,0x81005 +80001718: 9e878613 addi a2,a5,-1560 # 810049e8 +8000171c: 810047b7 lui a5,0x81004 +80001720: 9e878593 addi a1,a5,-1560 # 810039e8 +80001724: 810037b7 lui a5,0x81003 +80001728: 9e878513 addi a0,a5,-1560 # 810029e8 +8000172c: 94cff0ef jal ra,80000878 +80001730: 810007b7 lui a5,0x81000 +80001734: 16078513 addi a0,a5,352 # 81000160 +80001738: ff9fe0ef jal ra,80000730 +8000173c: 810057b7 lui a5,0x81005 +80001740: 9e878513 addi a0,a5,-1560 # 810049e8 +80001744: f11ff0ef jal ra,80001654 +80001748: 01000713 li a4,16 +8000174c: 01000693 li a3,16 +80001750: 810057b7 lui a5,0x81005 +80001754: 9e878613 addi a2,a5,-1560 # 810049e8 +80001758: 810047b7 lui a5,0x81004 +8000175c: 9e878593 addi a1,a5,-1560 # 810039e8 +80001760: 810037b7 lui a5,0x81003 +80001764: 9e878513 addi a0,a5,-1560 # 810029e8 +80001768: c10ff0ef jal ra,80000b78 +8000176c: 810007b7 lui a5,0x81000 +80001770: 17c78513 addi a0,a5,380 # 8100017c +80001774: fbdfe0ef jal ra,80000730 +80001778: 810057b7 lui a5,0x81005 +8000177c: 9e878513 addi a0,a5,-1560 # 810049e8 +80001780: ed5ff0ef jal ra,80001654 +80001784: 01000713 li a4,16 +80001788: 01000693 li a3,16 +8000178c: 810057b7 lui a5,0x81005 +80001790: 9e878613 addi a2,a5,-1560 # 810049e8 +80001794: 810047b7 lui a5,0x81004 +80001798: 9e878593 addi a1,a5,-1560 # 810039e8 +8000179c: 810037b7 lui a5,0x81003 +800017a0: 9e878513 addi a0,a5,-1560 # 810029e8 +800017a4: e74ff0ef jal ra,80000e18 +800017a8: 810007b7 lui a5,0x81000 +800017ac: 19078513 addi a0,a5,400 # 81000190 +800017b0: f81fe0ef jal ra,80000730 +800017b4: 810057b7 lui a5,0x81005 +800017b8: 9e878513 addi a0,a5,-1560 # 810049e8 +800017bc: e99ff0ef jal ra,80001654 +800017c0: 00300793 li a5,3 +800017c4: fef42623 sw a5,-20(s0) +800017c8: fec40593 addi a1,s0,-20 +800017cc: 01000713 li a4,16 +800017d0: 01000693 li a3,16 +800017d4: 810057b7 lui a5,0x81005 +800017d8: 9e878613 addi a2,a5,-1560 # 810049e8 +800017dc: 810057b7 lui a5,0x81005 +800017e0: 9e878513 addi a0,a5,-1560 # 810049e8 +800017e4: 8d5ff0ef jal ra,800010b8 +800017e8: 810007b7 lui a5,0x81000 +800017ec: 1a878513 addi a0,a5,424 # 810001a8 +800017f0: f41fe0ef jal ra,80000730 +800017f4: 810057b7 lui a5,0x81005 +800017f8: 9e878513 addi a0,a5,-1560 # 810049e8 +800017fc: e59ff0ef jal ra,80001654 +80001800: fec40593 addi a1,s0,-20 +80001804: 01000713 li a4,16 +80001808: 01000693 li a3,16 +8000180c: 810057b7 lui a5,0x81005 +80001810: 9e878613 addi a2,a5,-1560 # 810049e8 +80001814: 810057b7 lui a5,0x81005 +80001818: 9e878513 addi a0,a5,-1560 # 810049e8 +8000181c: b31ff0ef jal ra,8000134c +80001820: 810007b7 lui a5,0x81000 +80001824: 1a878513 addi a0,a5,424 # 810001a8 +80001828: f09fe0ef jal ra,80000730 +8000182c: 810057b7 lui a5,0x81005 +80001830: 9e878513 addi a0,a5,-1560 # 810049e8 +80001834: e21ff0ef jal ra,80001654 +80001838: 00000793 li a5,0 +8000183c: 00078513 mv a0,a5 +80001840: 01c12083 lw ra,28(sp) +80001844: 01812403 lw s0,24(sp) +80001848: 02010113 addi sp,sp,32 +8000184c: 00008067 ret + +Disassembly of section .rodata: + +81000000 <.rodata>: +81000000: 0030 addi a2,sp,8 +81000002: 0000 unimp +81000004: 0031 c.nop 12 +81000006: 0000 unimp +81000008: 0032 c.slli zero,0xc +8100000a: 0000 unimp +8100000c: 00000033 add zero,zero,zero +81000010: 0034 addi a3,sp,8 +81000012: 0000 unimp +81000014: 0035 c.nop 13 +81000016: 0000 unimp +81000018: 0036 c.slli zero,0xd +8100001a: 0000 unimp +8100001c: 00000037 lui zero,0x0 +81000020: 0038 addi a4,sp,8 +81000022: 0000 unimp +81000024: 0039 c.nop 14 +81000026: 0000 unimp +81000028: 0061 c.nop 24 +8100002a: 0000 unimp +8100002c: 0062 c.slli zero,0x18 +8100002e: 0000 unimp +81000030: 00000063 beqz zero,81000030 +81000034: 0064 addi s1,sp,12 +81000036: 0000 unimp +81000038: 0065 c.nop 25 +8100003a: 0000 unimp +8100003c: 0066 c.slli zero,0x19 +8100003e: 0000 unimp +81000040: 0030 addi a2,sp,8 +81000042: 0000 unimp +81000044: 0031 c.nop 12 +81000046: 0000 unimp +81000048: 0032 c.slli zero,0xc +8100004a: 0000 unimp +8100004c: 00000033 add zero,zero,zero +81000050: 0034 addi a3,sp,8 +81000052: 0000 unimp +81000054: 0035 c.nop 13 +81000056: 0000 unimp +81000058: 0036 c.slli zero,0xd +8100005a: 0000 unimp +8100005c: 00000037 lui zero,0x0 +81000060: 0038 addi a4,sp,8 +81000062: 0000 unimp +81000064: 0039 c.nop 14 +81000066: 0000 unimp +81000068: 0061 c.nop 24 +8100006a: 0000 unimp +8100006c: 0062 c.slli zero,0x18 +8100006e: 0000 unimp +81000070: 00000063 beqz zero,81000070 +81000074: 0064 addi s1,sp,12 +81000076: 0000 unimp +81000078: 0065 c.nop 25 +8100007a: 0000 unimp +8100007c: 0066 c.slli zero,0x19 +8100007e: 0000 unimp +81000080: 000a c.slli zero,0x2 +81000082: 0000 unimp +81000084: 0030 addi a2,sp,8 +81000086: 0000 unimp +81000088: 0031 c.nop 12 +8100008a: 0000 unimp +8100008c: 0032 c.slli zero,0xc +8100008e: 0000 unimp +81000090: 00000033 add zero,zero,zero +81000094: 0034 addi a3,sp,8 +81000096: 0000 unimp +81000098: 0035 c.nop 13 +8100009a: 0000 unimp +8100009c: 0036 c.slli zero,0xd +8100009e: 0000 unimp +810000a0: 00000037 lui zero,0x0 +810000a4: 0038 addi a4,sp,8 +810000a6: 0000 unimp +810000a8: 0039 c.nop 14 +810000aa: 0000 unimp +810000ac: 0061 c.nop 24 +810000ae: 0000 unimp +810000b0: 0062 c.slli zero,0x18 +810000b2: 0000 unimp +810000b4: 00000063 beqz zero,810000b4 +810000b8: 0064 addi s1,sp,12 +810000ba: 0000 unimp +810000bc: 0065 c.nop 25 +810000be: 0000 unimp +810000c0: 0066 c.slli zero,0x19 +810000c2: 0000 unimp +810000c4: 7366664f fnmadd.d fa2,fa2,fs6,fa4,unknown +810000c8: 7465 lui s0,0xffff9 +810000ca: 203a fld ft0,392(sp) +810000cc: 0000 unimp +810000ce: 0000 unimp +810000d0: 0030 addi a2,sp,8 +810000d2: 0000 unimp +810000d4: 0031 c.nop 12 +810000d6: 0000 unimp +810000d8: 0032 c.slli zero,0xc +810000da: 0000 unimp +810000dc: 00000033 add zero,zero,zero +810000e0: 0034 addi a3,sp,8 +810000e2: 0000 unimp +810000e4: 0035 c.nop 13 +810000e6: 0000 unimp +810000e8: 0036 c.slli zero,0xd +810000ea: 0000 unimp +810000ec: 00000037 lui zero,0x0 +810000f0: 0038 addi a4,sp,8 +810000f2: 0000 unimp +810000f4: 0039 c.nop 14 +810000f6: 0000 unimp +810000f8: 0061 c.nop 24 +810000fa: 0000 unimp +810000fc: 0062 c.slli zero,0x18 +810000fe: 0000 unimp +81000100: 00000063 beqz zero,81000100 +81000104: 0064 addi s1,sp,12 +81000106: 0000 unimp +81000108: 0065 c.nop 25 +8100010a: 0000 unimp +8100010c: 0066 c.slli zero,0x19 +8100010e: 0000 unimp +81000110: 2d2d jal 8100074a +81000112: 2d2d jal 8100074c +81000114: 2d2d jal 8100074e +81000116: 2d2d jal 81000750 +81000118: 2d2d jal 81000752 +8100011a: 2d2d jal 81000754 +8100011c: 2d2d jal 81000756 +8100011e: 2d2d jal 81000758 +81000120: 2d2d jal 8100075a +81000122: 2d2d jal 8100075c +81000124: 2d2d jal 8100075e +81000126: 2d2d jal 81000760 +81000128: 2d2d jal 81000762 +8100012a: 2d2d jal 81000764 +8100012c: 2d2d jal 81000766 +8100012e: 0a2d addi s4,s4,11 +81000130: 0000 unimp +81000132: 0000 unimp +81000134: 000a c.slli zero,0x2 +81000136: 0000 unimp +81000138: 0020 addi s0,sp,8 +8100013a: 0000 unimp +8100013c: 2d0a fld fs10,128(sp) +8100013e: 2d2d jal 81000778 +81000140: 2d2d jal 8100077a +81000142: 2d2d jal 8100077c +81000144: 2d2d jal 8100077e +81000146: 2d2d jal 81000780 +81000148: 2d2d jal 81000782 +8100014a: 2d2d jal 81000784 +8100014c: 2d2d jal 81000786 +8100014e: 2d2d jal 81000788 +81000150: 2d2d jal 8100078a +81000152: 2d2d jal 8100078c +81000154: 2d2d jal 8100078e +81000156: 2d2d jal 81000790 +81000158: 2d2d jal 81000792 +8100015a: 2d2d jal 81000794 +8100015c: 000a c.slli zero,0x2 +8100015e: 0000 unimp +81000160: 0a0a slli s4,s4,0x2 +81000162: 614d addi sp,sp,176 +81000164: 7274 flw fa3,100(a2) +81000166: 7869 lui a6,0xffffa +81000168: 6d20 flw fs0,88(a0) +8100016a: 6c75 lui s8,0x1d +8100016c: 6974 flw fa3,84(a0) +8100016e: 6c70 flw fa2,92(s0) +81000170: 6369 lui t1,0x1a +81000172: 7461 lui s0,0xffff8 +81000174: 6f69 lui t5,0x1a +81000176: 0a6e slli s4,s4,0x1b +81000178: 0000 unimp +8100017a: 0000 unimp +8100017c: 0a0a slli s4,s4,0x2 +8100017e: 614d addi sp,sp,176 +81000180: 7274 flw fa3,100(a2) +81000182: 7869 lui a6,0xffffa +81000184: 4120 lw s0,64(a0) +81000186: 6464 flw fs1,76(s0) +81000188: 7469 lui s0,0xffffa +8100018a: 6f69 lui t5,0x1a +8100018c: 0a6e slli s4,s4,0x1b +8100018e: 0000 unimp +81000190: 0a0a slli s4,s4,0x2 +81000192: 614d addi sp,sp,176 +81000194: 7274 flw fa3,100(a2) +81000196: 7869 lui a6,0xffffa +81000198: 5320 lw s0,96(a4) +8100019a: 6275 lui tp,0x1d +8100019c: 7274 flw fa3,100(a2) +8100019e: 6361 lui t1,0x18 +810001a0: 6974 flw fa3,84(a0) +810001a2: 000a6e6f jal t3,810a61a2 +810001a6: 0000 unimp +810001a8: 0a0a slli s4,s4,0x2 +810001aa: 614d addi sp,sp,176 +810001ac: 7274 flw fa3,100(a2) +810001ae: 7869 lui a6,0xffffa +810001b0: 4520 lw s0,72(a0) +810001b2: 656c flw fa1,76(a0) +810001b4: 656d lui a0,0x1b +810001b6: 746e flw fs0,248(sp) +810001b8: 4120 lw s0,64(a0) +810001ba: 6464 flw fs1,76(s0) +810001bc: 7469 lui s0,0xffffa +810001be: 6f69 lui t5,0x1a +810001c0: 0a6e slli s4,s4,0x1b + ... + +Disassembly of section .data: + +810001c4 : +810001c4: 0000 unimp +810001c6: 8100 0x8100 +810001c8: 0004 0x4 +810001ca: 8100 0x8100 +810001cc: 0008 0x8 +810001ce: 8100 0x8100 +810001d0: 000c 0xc +810001d2: 8100 0x8100 +810001d4: 0010 0x10 +810001d6: 8100 0x8100 +810001d8: 0014 0x14 +810001da: 8100 0x8100 +810001dc: 0018 0x18 +810001de: 8100 0x8100 +810001e0: 001c 0x1c +810001e2: 8100 0x8100 +810001e4: 0020 addi s0,sp,8 +810001e6: 8100 0x8100 +810001e8: 0024 addi s1,sp,8 +810001ea: 8100 0x8100 +810001ec: 0028 addi a0,sp,8 +810001ee: 8100 0x8100 +810001f0: 002c addi a1,sp,8 +810001f2: 8100 0x8100 +810001f4: 0030 addi a2,sp,8 +810001f6: 8100 0x8100 +810001f8: 0034 addi a3,sp,8 +810001fa: 8100 0x8100 +810001fc: 0038 addi a4,sp,8 +810001fe: 8100 0x8100 +81000200: 003c addi a5,sp,8 +81000202: 8100 0x8100 + +81000204 : +81000204: 0040 addi s0,sp,4 +81000206: 8100 0x8100 +81000208: 0044 addi s1,sp,4 +8100020a: 8100 0x8100 +8100020c: 0048 addi a0,sp,4 +8100020e: 8100 0x8100 +81000210: 004c addi a1,sp,4 +81000212: 8100 0x8100 +81000214: 0050 addi a2,sp,4 +81000216: 8100 0x8100 +81000218: 0054 addi a3,sp,4 +8100021a: 8100 0x8100 +8100021c: 0058 addi a4,sp,4 +8100021e: 8100 0x8100 +81000220: 005c addi a5,sp,4 +81000222: 8100 0x8100 +81000224: 0060 addi s0,sp,12 +81000226: 8100 0x8100 +81000228: 0064 addi s1,sp,12 +8100022a: 8100 0x8100 +8100022c: 0068 addi a0,sp,12 +8100022e: 8100 0x8100 +81000230: 006c addi a1,sp,12 +81000232: 8100 0x8100 +81000234: 0070 addi a2,sp,12 +81000236: 8100 0x8100 +81000238: 0074 addi a3,sp,12 +8100023a: 8100 0x8100 +8100023c: 0078 addi a4,sp,12 +8100023e: 8100 0x8100 +81000240: 007c addi a5,sp,12 +81000242: 8100 0x8100 + +81000244 : +81000244: 0084 addi s1,sp,64 +81000246: 8100 0x8100 +81000248: 0088 addi a0,sp,64 +8100024a: 8100 0x8100 +8100024c: 008c addi a1,sp,64 +8100024e: 8100 0x8100 +81000250: 0090 addi a2,sp,64 +81000252: 8100 0x8100 +81000254: 0094 addi a3,sp,64 +81000256: 8100 0x8100 +81000258: 0098 addi a4,sp,64 +8100025a: 8100 0x8100 +8100025c: 009c addi a5,sp,64 +8100025e: 8100 0x8100 +81000260: 00a0 addi s0,sp,72 +81000262: 8100 0x8100 +81000264: 00a4 addi s1,sp,72 +81000266: 8100 0x8100 +81000268: 00a8 addi a0,sp,72 +8100026a: 8100 0x8100 +8100026c: 00ac addi a1,sp,72 +8100026e: 8100 0x8100 +81000270: 00b0 addi a2,sp,72 +81000272: 8100 0x8100 +81000274: 00b4 addi a3,sp,72 +81000276: 8100 0x8100 +81000278: 00b8 addi a4,sp,72 +8100027a: 8100 0x8100 +8100027c: 00bc addi a5,sp,72 +8100027e: 8100 0x8100 +81000280: 00c0 addi s0,sp,68 +81000282: 8100 0x8100 + +81000284 : +81000284: 00d0 addi a2,sp,68 +81000286: 8100 0x8100 +81000288: 00d4 addi a3,sp,68 +8100028a: 8100 0x8100 +8100028c: 00d8 addi a4,sp,68 +8100028e: 8100 0x8100 +81000290: 00dc addi a5,sp,68 +81000292: 8100 0x8100 +81000294: 00e0 addi s0,sp,76 +81000296: 8100 0x8100 +81000298: 00e4 addi s1,sp,76 +8100029a: 8100 0x8100 +8100029c: 00e8 addi a0,sp,76 +8100029e: 8100 0x8100 +810002a0: 00ec addi a1,sp,76 +810002a2: 8100 0x8100 +810002a4: 00f0 addi a2,sp,76 +810002a6: 8100 0x8100 +810002a8: 00f4 addi a3,sp,76 +810002aa: 8100 0x8100 +810002ac: 00f8 addi a4,sp,76 +810002ae: 8100 0x8100 +810002b0: 00fc addi a5,sp,76 +810002b2: 8100 0x8100 +810002b4: 0100 addi s0,sp,128 +810002b6: 8100 0x8100 +810002b8: 0104 addi s1,sp,128 +810002ba: 8100 0x8100 +810002bc: 0108 addi a0,sp,128 +810002be: 8100 0x8100 +810002c0: 010c addi a1,sp,128 +810002c2: 8100 0x8100 + +Disassembly of section .bss: + +810002c4 : + ... + +810002e0 : +810002e0: 0000 unimp + ... + +810002e4 : + ... + +81000364 : + ... + +81002984 : + ... + +810029a0 : +810029a0: 0000 unimp + ... + +810029a4 : + ... + +810029b8 : + ... + +810029d0 : + ... + +810029e8 : + ... + +810039e8 : + ... + +810049e8 : + ... + +810059e8 : + ... + +81005a04 : +81005a04: 0000 unimp + ... + +Disassembly of section .comment: + +82000000 <.comment>: +82000000: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm +82000004: 2820 fld fs0,80(s0) +82000006: 29554e47 fmsub.s ft8,fa0,fs5,ft5,rmm +8200000a: 3820 fld fs0,112(s0) +8200000c: 322e fld ft4,232(sp) +8200000e: 302e fld ft0,232(sp) + ... diff --git a/kernel/vortex_test.elf b/kernel/vortex_test.elf new file mode 100755 index 00000000..6482f6dd Binary files /dev/null and b/kernel/vortex_test.elf differ diff --git a/kernel/vortex_test.hex b/kernel/vortex_test.hex new file mode 100644 index 00000000..669b4b87 --- /dev/null +++ b/kernel/vortex_test.hex @@ -0,0 +1,438 @@ +:0200000480007A +:1000000013054000731005021305800073101502DC +:10001000731040F17310103037F1FF7FEF0080193B +:10002000EF10C06D73000000938B0600130D0700E6 +:10003000130F01009303050013051000635C7500A6 +:1000400013010180130305006B5003001305150015 +:100050006FF0DFFE13010F0013050000930F060081 +:10006000938D0300EBE0BF01170500001305051B8E +:100070006B40050017030000130343FB6B000300F4 +:1000800067800000170200011302022623200200ED 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+:1002440084000081880000818C000081900000817E +:1002540094000081980000819C000081A00000812E +:10026400A4000081A8000081AC000081B0000081DE +:10027400B4000081B8000081BC000081C00000818E +:10028400D0000081D4000081D8000081DC0000810E +:10029400E0000081E4000081E8000081EC000081BE +:1002A400F0000081F4000081F8000081FC0000816E +:1002B4000001008104010081080100810C0100811A +:040000058000000077 +:00000001FF diff --git a/kernel/vx_include/.DS_Store b/kernel/vx_include/.DS_Store new file mode 100644 index 00000000..f03454ae Binary files /dev/null and b/kernel/vx_include/.DS_Store differ diff --git a/kernel/vx_include/vx_front.c b/kernel/vx_include/vx_front.c new file mode 100644 index 00000000..c64db4c7 --- /dev/null +++ b/kernel/vx_include/vx_front.c @@ -0,0 +1,439 @@ + +#include "vx_front.h" +#include "../vx_os/vx_back/vx_back.h" + +// -------------------------- Matrix Multiplication -------------------------- + +static mat_mult_arg_t mat_mult_args; + +void _vx_mat_mult(unsigned, unsigned); +void vx_sq_mat_mult(void * x, void * y, void * z, unsigned mat_dim) +{ + mat_mult_args.x = x; + mat_mult_args.y = y; + mat_mult_args.z = z; + mat_mult_args.mat_dim = mat_dim; + + unsigned num_avail_threads = vx_available_threads(); + + unsigned off = (mat_dim/num_avail_threads); + + if ((mat_dim%num_avail_threads) != 0) + { + off += 1; + } + + vx_printf("Offset: ", off); + + + mat_mult_args.offset = off; + + if (mat_dim >= num_avail_threads) + { + vx_spawnWarps(mat_dim, num_avail_threads, _vx_mat_mult, (void *) (&mat_mult_args)); + } + else + { + vx_spawnWarps(mat_dim, mat_dim, _vx_mat_mult, (void *) (&mat_mult_args)); + } + + unsigned num_avail_warps = vx_available_warps(); + + if (mat_dim > num_avail_warps) + { + vx_wait_for_warps(num_avail_warps); + } + else + { + vx_wait_for_warps(mat_dim); + } +} + +void _vx_mat_mult(unsigned tid, unsigned wid) +{ + mat_mult_arg_t * args = (mat_mult_arg_t *) vx_get_arg_struct(); + + unsigned * x_ptr = args->x; + unsigned * y_ptr = args->y; + unsigned * z_ptr = args->z; + + unsigned off = args->offset; + + unsigned i_index = off * tid; + + if (off == 0) + { + off = 1; + i_index = tid; + } + + unsigned mat_dim = args->mat_dim; + + for (int iter = 0; iter < off; ++iter) + { + unsigned total = 0; + for (unsigned place = 0; place < mat_dim; ++place) + { + unsigned x_i = (wid * mat_dim) + place; + unsigned y_i = (mat_dim * place) + i_index; + + total += (x_ptr[x_i] * y_ptr[y_i]); + } + + int final_i = (wid * mat_dim) + i_index; + unsigned cond = i_index < mat_dim; + __if(cond) + { + z_ptr[final_i] = total; + i_index++; + } + __else + __end_if + } + + // for (int z = 0; z < ((1000 * wid) + 1000); z++); + return; +} + + + + +static mat_r_arg_t mat_r_args; +// -------------------------- Matrix Addition -------------------------- +void _vx_mat_add(unsigned, unsigned); +void vx_mat_add(void * x, void * y, void * z, unsigned num_rows, unsigned num_cols) +{ + mat_r_args.x = x; + mat_r_args.y = y; + mat_r_args.z = z; + mat_r_args.num_cols = num_cols; + mat_r_args.num_rows = num_rows; + + + unsigned num_avail_threads = vx_available_threads(); + + unsigned off = (num_cols/num_avail_threads); + + if ((num_cols%num_avail_threads) != 0) + { + off += 1; + } + + + mat_r_args.offset = off; + + if (num_cols >= num_avail_threads) + { + vx_spawnWarps(num_rows, num_avail_threads, _vx_mat_add, (void *) (&mat_r_args)); + } + else + { + vx_spawnWarps(num_rows, num_cols, _vx_mat_add, (void *) (&mat_r_args)); + } + + unsigned num_avail_warps = vx_available_warps(); + + if (num_rows > num_avail_warps) + { + vx_wait_for_warps(num_avail_warps); + } + else + { + vx_wait_for_warps(num_rows); + } +} + +void _vx_mat_add(unsigned tid, unsigned wid) +{ + // vx_print_str("*"); + // for (int z = 0; z < ((wid * 1000) + 1000); z++); + + mat_r_arg_t * args = (mat_r_arg_t *) vx_get_arg_struct(); + + unsigned * x_ptr = args->x; + unsigned * y_ptr = args->y; + unsigned * z_ptr = args->z; + + unsigned off = args->offset; + + unsigned i_index = off * tid; + + if (off == 0) + { + off = 1; + i_index = tid; + } + + unsigned num_cols = args->num_cols; + + for (int iter = 0; iter < off; ++iter) + { + int final_i = (wid * num_cols) + i_index; + unsigned cond = i_index < num_cols; + __if(cond) + { + z_ptr[final_i] = x_ptr[final_i] + y_ptr[final_i]; + i_index++; + } + __else + __end_if + } + return; + +} + + + +// -------------------------- Matrix Subtraction -------------------------- +void _vx_mat_sub(unsigned, unsigned); +void vx_mat_sub(void * x, void * y, void * z, unsigned num_rows, unsigned num_cols) +{ + mat_r_args.x = x; + mat_r_args.y = y; + mat_r_args.z = z; + mat_r_args.num_cols = num_cols; + mat_r_args.num_rows = num_rows; + + unsigned num_avail_threads = vx_available_threads(); + + unsigned off = (num_cols/num_avail_threads); + + if ((num_cols%num_avail_threads) != 0) + { + off += 1; + } + + + mat_r_args.offset = off; + + if (num_cols >= num_avail_threads) + { + vx_spawnWarps(num_rows, num_avail_threads, _vx_mat_sub, (void *) (&mat_r_args)); + } + else + { + vx_spawnWarps(num_rows, num_cols, _vx_mat_sub, (void *) (&mat_r_args)); + } + + unsigned num_avail_warps = vx_available_warps(); + + if (num_rows > num_avail_warps) + { + vx_wait_for_warps(num_avail_warps); + } + else + { + vx_wait_for_warps(num_rows); + } +} + +void _vx_mat_sub(unsigned tid, unsigned wid) +{ + // vx_print_str("*"); + // for (int z = 0; z < ((wid * 1000) + 1000); z++); + + mat_r_arg_t * args = (mat_r_arg_t *) vx_get_arg_struct(); + + unsigned * x_ptr = args->x; + unsigned * y_ptr = args->y; + unsigned * z_ptr = args->z; + + unsigned off = args->offset; + + unsigned i_index = off * tid; + + if (off == 0) + { + off = 1; + i_index = tid; + } + + unsigned num_cols = args->num_cols; + + for (int iter = 0; iter < off; ++iter) + { + int final_i = (wid * num_cols) + i_index; + unsigned cond = i_index < num_cols; + __if(cond) + { + z_ptr[final_i] = x_ptr[final_i] - y_ptr[final_i]; + i_index++; + } + __else + __end_if + } + return; + +} + + + +static mat_e_arg_t mat_e_args; +// -------------------------------------------------------------- + +void _vx_e_mat_add(unsigned, unsigned); +void vx_e_mat_add(void * x, void * scal, void * z, unsigned num_rows, unsigned num_cols) +{ + mat_e_args.x = x; + mat_e_args.scal = scal; + mat_e_args.z = z; + mat_e_args.num_cols = num_cols; + mat_e_args.num_rows = num_rows; + + + unsigned num_avail_threads = vx_available_threads(); + + unsigned off = (num_cols/num_avail_threads); + + if ((num_cols%num_avail_threads) != 0) + { + off += 1; + } + + mat_e_args.offset = off; + + if (num_cols >= num_avail_threads) + { + vx_spawnWarps(num_rows, num_avail_threads, _vx_e_mat_add, (void *) (&mat_e_args)); + } + else + { + vx_spawnWarps(num_rows, num_cols, _vx_e_mat_add, (void *) (&mat_e_args)); + } + + unsigned num_avail_warps = vx_available_warps(); + + if (num_rows > num_avail_warps) + { + vx_wait_for_warps(num_avail_warps); + } + else + { + vx_wait_for_warps(num_rows); + } +} + +void _vx_e_mat_add(unsigned tid, unsigned wid) +{ + // vx_print_str("*"); + // for (int z = 0; z < ((wid * 1000) + 1000); z++); + + mat_e_arg_t * args = (mat_e_arg_t *) vx_get_arg_struct(); + + unsigned * x_ptr = args->x; + unsigned scal = *((unsigned *) args->scal); + + unsigned * z_ptr = args->z; + + unsigned off = args->offset; + + unsigned i_index = off * tid; + + if (off == 0) + { + off = 1; + i_index = tid; + } + + unsigned num_cols = args->num_cols; + + for (int iter = 0; iter < off; ++iter) + { + int final_i = (wid * num_cols) + i_index; + unsigned cond = i_index < num_cols; + __if(cond) + { + z_ptr[final_i] = x_ptr[final_i] + scal; + i_index++; + } + __else + __end_if + } + return; + +} + +void _vx_e_mat_mult(unsigned, unsigned); +void vx_e_mat_mult(void * x, void * scal, void * z, unsigned num_rows, unsigned num_cols) +{ + mat_e_args.x = x; + mat_e_args.scal = scal; + mat_e_args.z = z; + mat_e_args.num_cols = num_cols; + mat_e_args.num_rows = num_rows; + + + unsigned num_avail_threads = vx_available_threads(); + + unsigned off = (num_cols/num_avail_threads); + + if ((num_cols%num_avail_threads) != 0) + { + off += 1; + } + + mat_e_args.offset = off; + + if (num_cols >= num_avail_threads) + { + vx_spawnWarps(num_rows, num_avail_threads, _vx_e_mat_mult, (void *) (&mat_e_args)); + } + else + { + vx_spawnWarps(num_rows, num_cols, _vx_e_mat_mult, (void *) (&mat_e_args)); + } + + unsigned num_avail_warps = vx_available_warps(); + + if (num_rows > num_avail_warps) + { + vx_wait_for_warps(num_avail_warps); + } + else + { + vx_wait_for_warps(num_rows); + } +} + +void _vx_e_mat_mult(unsigned tid, unsigned wid) +{ + // vx_print_str("*"); + // for (int z = 0; z < ((wid * 1000) + 1000); z++); + + mat_e_arg_t * args = (mat_e_arg_t *) vx_get_arg_struct(); + + unsigned * x_ptr = args->x; + unsigned scal = *((unsigned *) args->scal); + + unsigned * z_ptr = args->z; + + unsigned off = args->offset; + + unsigned i_index = off * tid; + + if (off == 0) + { + off = 1; + i_index = tid; + } + + unsigned num_cols = args->num_cols; + + for (int iter = 0; iter < off; ++iter) + { + int final_i = (wid * num_cols) + i_index; + unsigned cond = i_index < num_cols; + __if(cond) + { + z_ptr[final_i] = x_ptr[final_i] * scal; + i_index++; + } + __else + __end_if + } + return; + +} + + + diff --git a/kernel/vx_include/vx_front.h b/kernel/vx_include/vx_front.h new file mode 100644 index 00000000..b78b8284 --- /dev/null +++ b/kernel/vx_include/vx_front.h @@ -0,0 +1,55 @@ +#include "../vx_os/vx_back/vx_back.h" +#include "../vx_os/vx_io/vx_io.h" + + +// -------------------------- Matrix Multiplication -------------------------- + +typedef struct +{ + void * x; + void * y; + void * z; + unsigned mat_dim; + unsigned offset; + +} mat_mult_arg_t; +void vx_sq_mat_mult(void *, void *, void *, unsigned); + + +// -------------------------------------------------------------------------- + +typedef struct +{ + void * x; + void * y; + void * z; + unsigned num_cols; + unsigned num_rows; + unsigned offset; + +} mat_r_arg_t; +// -------------------------- Matrix Addition ----------------------------- +void vx_mat_add(void *, void *, void *, unsigned, unsigned); + +// -------------------------- Matrix Subtraction -------------------------- +void vx_mat_sub(void *, void *, void *, unsigned, unsigned); + + + +// ----------------------------------------------------------------------- +typedef struct +{ + void * x; + void * scal; + void * z; + unsigned num_cols; + unsigned num_rows; + unsigned offset; + +} mat_e_arg_t; + +// -------------------------- Matrix element Addition ------------------ +void vx_e_mat_add(void *, void *, void *, unsigned, unsigned); + +// -------------------------- Matrix element Addition ------------------ +void vx_e_mat_mult(void *, void *, void *, unsigned, unsigned); \ No newline at end of file diff --git a/kernel/vx_main.c b/kernel/vx_main.c new file mode 100644 index 00000000..0d70faad --- /dev/null +++ b/kernel/vx_main.c @@ -0,0 +1,70 @@ + +#include "./vx_include/vx_front.h" + +unsigned x[1024] = {0}; +unsigned y[1024] = {0}; +unsigned z[1024] = {0}; + +#define MAT_DIM 16 + +#define NUM_COLS 16 +#define NUM_ROWS 16 + +void initialize_mats() +{ + for (int i = 0; i < (MAT_DIM * MAT_DIM); i++) + { + x[i] = 3; + y[i] = 2; + } +} + +void print_matrix(unsigned * z) +{ + vx_print_str("-------------------------------\n"); + for (int j = 0; j < (MAT_DIM * MAT_DIM); j++) + { + if (j!=0) if ((j % MAT_DIM) == 0) vx_print_str("\n"); + vx_print_hex(z[j]); + vx_print_str(" "); + } + vx_print_str("\n-------------------------------\n"); +} + +int main() +{ + + initialize_mats(); + + // matrix multiplication + vx_sq_mat_mult(x, y, z, MAT_DIM); + vx_print_str("\n\nMatrix multiplication\n"); + print_matrix(z); + + + // matrix addition + vx_mat_add(x, y, z, NUM_ROWS, NUM_COLS); + vx_print_str("\n\nMatrix Addition\n"); + print_matrix(z); + + + // matrix sub + vx_mat_sub(x, y, z, NUM_ROWS, NUM_COLS); + vx_print_str("\n\nMatrix Subtraction\n"); + print_matrix(z); + + unsigned scal = 3; + + // matrix element add + vx_e_mat_add(z, &scal, z, NUM_ROWS, NUM_COLS); + vx_print_str("\n\nMatrix Element Addition\n"); + print_matrix(z); + + // matrix element add + vx_e_mat_mult(z, &scal, z, NUM_ROWS, NUM_COLS); + vx_print_str("\n\nMatrix Element Addition\n"); + print_matrix(z); + + + return 0; +} \ No newline at end of file diff --git a/kernel/vx_os/.DS_Store b/kernel/vx_os/.DS_Store new file mode 100644 index 00000000..b0526ab1 Binary files /dev/null and b/kernel/vx_os/.DS_Store differ diff --git a/kernel/vx_os/vx_back/vx_back.c b/kernel/vx_os/vx_back/vx_back.c new file mode 100644 index 00000000..9f3d7cee --- /dev/null +++ b/kernel/vx_os/vx_back/vx_back.c @@ -0,0 +1,150 @@ + +#include "vx_back.h" +#include "../vx_io/vx_io.h" + + +void vx_before_main() +{ + // unsigned num_available_warps = vx_available_warps(); + for (int i = 0; i < 8; i++) + { + queue_initialize(q + i); + } +} + +void vx_reschedule_warps() +{ + + + register unsigned curr_warp asm("s10"); + // vx_printf("Reschedule: ", curr_warp); + + if (queue_isEmpty(q+curr_warp)) + { + // vx_printf("Done: ", curr_warp); + done[curr_warp] = 1; + if (curr_warp == 0) + { + vx_load_context(); + return; + } + ECALL; + } + + Job j; + queue_dequeue(q+curr_warp,&j); + + // vx_printf("Reschedule -> ", j.wid); + asm __volatile__("mv sp,%0"::"r" (j.base_sp):); + vx_createThreads(j.n_threads, j.wid, j.func_ptr, j.args, j.assigned_warp); + + ECALL; + +} + +void vx_schedule_warps() +{ + + unsigned num_available_warps = vx_available_warps(); + + asm __volatile__("mv s3, sp"); + + for (int curr_warp = 1; curr_warp < num_available_warps; ++curr_warp) + { + if (!queue_isEmpty(q+curr_warp)) + { + Job j; + queue_dequeue(q+curr_warp,&j); + asm __volatile__("mv sp,%0"::"r" (j.base_sp):); + vx_wspawn(j.n_threads, j.wid, j.func_ptr, j.args, j.assigned_warp); + } + } + + asm __volatile__("mv sp, s3"); + + + vx_save_context(); + + // vx_print_str("saved context\n"); + + register unsigned val asm("tp"); + if (val) + { + if (!queue_isEmpty(q)) + { + // vx_print_str("found something for w0\n"); + Job j; + queue_dequeue(q,&j); + // vx_printf("num_threads: ", j.n_threads); + asm __volatile__("mv sp,%0"::"r" (j.base_sp):); + vx_createThreads(j.n_threads, j.wid, j.func_ptr, j.args, j.assigned_warp); + } + } + +} + + +void vx_spawnWarps(unsigned num_Warps, unsigned num_threads, FUNC, void * args) +{ + vx_before_main(); + + unsigned num_available_warps = vx_available_warps(); + // vx_printf("Num available warps: ", num_available_warps); + + asm __volatile__("addi s2, sp, 0"); + int warp = 0; + for (unsigned i = 0; i < num_Warps; i++) + { + asm __volatile__("lui s3, 0xFFFF0"); + asm __volatile__("add sp, sp, s3"); + register unsigned stack_ptr asm("sp"); + + Job j; + j.wid = i; + j.n_threads = num_threads; + j.base_sp = stack_ptr; + j.func_ptr = (unsigned) func; + j.args = args; + j.assigned_warp = warp; + + queue_enqueue(q + warp,&j); + ++warp; + if (warp >= num_available_warps) warp = 0; + } + asm __volatile__("addi sp, s2, 0"); + + + vx_schedule_warps(); + +} + +void vx_wait_for_warps(unsigned num_wait) +{ + // vx_printf("wait for: ", num_wait); + unsigned num_available_warps = vx_available_warps(); + unsigned num = 0; + while (num != num_wait) + { + num = 0; + for (int i = 0; i < num_available_warps; i++) + { + if (done[i] == 1) + { + num += 1; + } + } + } + + // vx_printf("num found: ", num); + for (int i = 0; i < num_available_warps; i++) done[i] = 0; +} + + +void * vx_get_arg_struct(void) +{ + register void *ret asm("s7"); + return ret; +} + + + diff --git a/kernel/vx_os/vx_back/vx_back.h b/kernel/vx_os/vx_back/vx_back.h new file mode 100644 index 00000000..c31b1dea --- /dev/null +++ b/kernel/vx_os/vx_back/vx_back.h @@ -0,0 +1,55 @@ + + +#pragma once + +#include +#include "../vx_util/queue.h" + +#define WSPAWN asm __volatile__(".word 0x3006b"::); +#define CLONE asm __volatile__(".word 0x3506b":::); +#define JALRS asm __volatile__(".word 0x1bfe0eb":::"s10"); +#define ECALL asm __volatile__(".word 0x00000073"); +#define JMPRT asm __volatile__(".word 0x5406b"); +#define SPLIT asm __volatile__(".word 0xf206b"); +#define P_JUMP asm __volatile__(".word 0x1ff707b"); +#define JOIN asm __volatile__(".word 0x306b"); + + +#define __if(val) bool temp = !val; \ + register unsigned p asm("t5") = temp; \ + register void * e asm("t6") = &&ELSE; \ + SPLIT; \ + P_JUMP; \ + + +#define __else register void * w asm("t3") = &&AFTER; \ + asm __volatile__("jr t3"); \ + ELSE: asm __volatile__("nop"); + +#define __end_if AFTER:\ + JOIN; + +static int done[] = {0, 0, 0, 0, 0, 0, 0}; + +static int main_sp[1]; + +unsigned context[32]; +void vx_save_context(void); +void vx_load_context(void); + + +#define FUNC void (func)(unsigned, unsigned) + +unsigned vx_available_warps(void); +unsigned vx_available_threads(void); + + +void vx_createThreads(unsigned, unsigned, unsigned, void *, unsigned); +void vx_wspawn(unsigned, unsigned, unsigned, void *, unsigned); +void vx_spawnWarps(unsigned num_Warps, unsigned num_threads, FUNC, void *); +void vx_schedule_warps(void); +void vx_reschedule_warps(void); +void vx_wait_for_warps(unsigned); +void * vx_get_arg_struct(void); + + diff --git a/kernel/vx_os/vx_back/vx_back.s b/kernel/vx_os/vx_back/vx_back.s new file mode 100644 index 00000000..c918588d --- /dev/null +++ b/kernel/vx_os/vx_back/vx_back.s @@ -0,0 +1,151 @@ + + + +.section .text + +.type _start, @function +.global _start +_start: + li a0, 4 # Num Warps + csrw 0x20, a0 # Setting the number of available warps + li a0, 8 # Num Threads + csrw 0x21, a0 # Setting the number of available threads + csrw mhartid,zero + csrw misa,zero + lui sp, 0x7ffff + jal vx_before_main + jal main + ecall + +.type vx_createThreads, @function +.global vx_createThreads +vx_createThreads: + mv s7 ,a3 # Moving args to s7 + mv s10,a4 # Moving assigned_warp to s10 + mv t5 ,sp # Saving the current stack pointer to t5 + mv t2 , a0 # t2 = num_threads +loop_init: + li a0,1 # i = 0 +loop_cond: + bge a0, t2, loop_done # i < num_threads +loop_body: + addi sp,sp,-2048 # Allocate 2k stack for new thread + mv t1, a0 # #lane = i + .word 0x3506b # clone register state +loop_inc: + addi a0, a0, 1 + j loop_cond +loop_done: + mv sp,t5 # Restoring the stack + li a0,0 # setting tid = 0 for main thread + mv t6,a2 # setting func_addr + mv s11,t2 # setting num_threads to spawn + .word 0x1bfe0eb + la a0, vx_reschedule_warps + .word 0x5406b + + +.type vx_wspawn, @function +.global vx_wspawn +vx_wspawn: + la t1, vx_createThreads + .word 0x3006b # WSPAWN instruction + ret + +.global context + +.type vx_save_context, @function +.global vx_save_context +vx_save_context: +la tp, context +sw x0 , 0 (tp) +sw x1 , 4 (tp) +sw x2 , 8 (tp) +sw x3 , 12(tp) +sw x4 , 16(tp) +sw x5 , 20(tp) +sw x6 , 24(tp) +sw x7 , 28(tp) +sw x8 , 32(tp) +sw x9 , 36(tp) +sw x10, 40(tp) +sw x11, 44(tp) +sw x12, 48(tp) +sw x13, 52(tp) +sw x14, 56(tp) +sw x15, 60(tp) +sw x16, 64(tp) +sw x17, 68(tp) +sw x18, 72(tp) +sw x19, 76(tp) +sw x20, 80(tp) +sw x21, 84(tp) +sw x22, 88(tp) +sw x23, 92(tp) +sw x24, 96(tp) +sw x25, 100(tp) +sw x26, 104(tp) +sw x27, 108(tp) +sw x28, 112(tp) +sw x29, 116(tp) +sw x30, 120(tp) +sw x31, 124(tp) +li tp, 1 +ret + + +.type vx_load_context, @function +.global vx_load_context +vx_load_context: +la tp, context +lw x0 , 0 (tp) +lw x1 , 4 (tp) +lw x2 , 8 (tp) +lw x3 , 12(tp) +lw x4 , 16(tp) +lw x5 , 20(tp) +lw x6 , 24(tp) +lw x7 , 28(tp) +lw x8 , 32(tp) +lw x9 , 36(tp) +lw x10, 40(tp) +lw x11, 44(tp) +lw x12, 48(tp) +lw x13, 52(tp) +lw x14, 56(tp) +lw x15, 60(tp) +lw x16, 64(tp) +lw x17, 68(tp) +lw x18, 72(tp) +lw x19, 76(tp) +lw x20, 80(tp) +lw x21, 84(tp) +lw x22, 88(tp) +lw x23, 92(tp) +lw x24, 96(tp) +lw x25, 100(tp) +lw x26, 104(tp) +lw x27, 108(tp) +lw x28, 112(tp) +lw x29, 116(tp) +lw x30, 120(tp) +lw x31, 124(tp) +li tp, 0 +ret + +.type vx_available_warps, @function +.global vx_available_warps +vx_available_warps: +csrr a0, 0x20 +ret + +.type vx_available_threads, @function +.global vx_available_threads +vx_available_threads: +csrr a0, 0x21 +ret + + + + + diff --git a/kernel/vx_os/vx_io/.DS_Store b/kernel/vx_os/vx_io/.DS_Store new file mode 100644 index 00000000..b23802d5 Binary files /dev/null and b/kernel/vx_os/vx_io/.DS_Store differ diff --git a/kernel/vx_os/vx_io/vx_io.c b/kernel/vx_os/vx_io/vx_io.c new file mode 100644 index 00000000..e86047b2 --- /dev/null +++ b/kernel/vx_os/vx_io/vx_io.c @@ -0,0 +1,29 @@ + +#include "vx_io.h" + +void vx_print_hex(unsigned f) +{ + if (f < 16) + { + vx_print_str(hextoa[f]); + return; + } + int temp; + int sf = 32; + bool start = false; + do + { + temp = (f >> (sf - 4)) & 0xf; + if (temp != 0) start = true; + if (start) vx_print_str(hextoa[temp]); + sf -= 4; + } while(sf > 0); +} + + +void vx_printf(char * c, unsigned f) +{ + vx_print_str(c); + vx_print_hex(f); + vx_print_str("\n"); +} \ No newline at end of file diff --git a/kernel/vx_os/vx_io/vx_io.h b/kernel/vx_os/vx_io/vx_io.h new file mode 100644 index 00000000..f3ed14f6 --- /dev/null +++ b/kernel/vx_os/vx_io/vx_io.h @@ -0,0 +1,9 @@ + +#pragma once + +#include + +static char * hextoa[] = {"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "a", "b", "c", "d", "e", "f"}; +void vx_print_hex(unsigned); +void vx_print_str(char *); +void vx_printf(char *, unsigned); \ No newline at end of file diff --git a/kernel/vx_os/vx_io/vx_io.s b/kernel/vx_os/vx_io/vx_io.s new file mode 100644 index 00000000..676b92bd --- /dev/null +++ b/kernel/vx_os/vx_io/vx_io.s @@ -0,0 +1,30 @@ + + +.type vx_print_str, @function +.global vx_print_str +vx_print_str: + addi sp, sp, -12 + sw ra, 0(sp) + sw a1, 4(sp) +bl: + lbu a1,0(a0) + beqz a1,be + jal vx_printc + addi a0, a0, 1 + j bl +be: + lw ra, 0(sp) + lw a1, 4(sp) + addi sp, sp, 12 + ret + + +.type vx_printc, @function +.global vx_printc +vx_printc: + la a7, 0x00010000 + sw a1, 0(a7) + ret + + + diff --git a/kernel/vx_os/vx_util/.DS_Store b/kernel/vx_os/vx_util/.DS_Store new file mode 100644 index 00000000..0ee024ad Binary files /dev/null and b/kernel/vx_os/vx_util/.DS_Store differ diff --git a/kernel/vx_os/vx_util/queue.h b/kernel/vx_os/vx_util/queue.h new file mode 100644 index 00000000..6793d467 --- /dev/null +++ b/kernel/vx_os/vx_util/queue.h @@ -0,0 +1,49 @@ + +#ifndef __QUEUE__ + +#define __QUEUE__ + + + +#define SIZE 50 +#define WARPS 7 + + +typedef struct Job_t +{ + unsigned wid; + unsigned n_threads; + unsigned base_sp; + unsigned func_ptr; + void * args; + unsigned assigned_warp; + +} Job; + +typedef struct Queue_t +{ + unsigned start_i; + unsigned end_i; + unsigned num_j; + unsigned total_warps; + unsigned active_warps; + struct Job_t jobs[SIZE]; + +} Queue; + +Queue q[8]; + +void queue_initialize(Queue *); + +void queue_enqueue(Queue *, Job *); + +void queue_dequeue(Queue *, Job *); + +int queue_isFull(Queue *); +int queue_isEmpty(Queue *); +int queue_availableWarps(Queue *); + + +void func(); + +#endif \ No newline at end of file diff --git a/kernel/vx_os/vx_util/queue.s b/kernel/vx_os/vx_util/queue.s new file mode 100644 index 00000000..6fcec494 --- /dev/null +++ b/kernel/vx_os/vx_util/queue.s @@ -0,0 +1,123 @@ + +.equ A_WARPS, 7 +.equ SIZE, 50 + +.section .text + +.type queue_initialize, @function +.global queue_initialize +queue_initialize: + mv t0, a0 # loading base address of q + li t1, 0 # to initialize variables + li t2, A_WARPS # Num of available warps + sw t1, 0 (t0) # start_i + sw t1, 4 (t0) # end_i + sw t1, 8 (t0) # num_j + sw t2, 12(t0) # total_warps + sw t1, 16(t0) # active_warps + ret + + + + +.type queue_enqueue, @function +.global queue_enqueue +queue_enqueue: + mv t0, a0 # loding base address of q + lw t1, 8 (t0) # t1 = num_j + addi t1, t1, 1 # ++t1 + sw t1, 8 (t0) # num_j = t1 + addi t1, t0, 20 # t1 = jobs_addr + lw t4, 4 (t0) # t4 = end_i + slli t2, t4, 5 # index * 32 [log(sizeof(job))] + add t1, t1, t2 # jobs + index + lw t3, 0 (a1) # wid + sw t3, 0 (t1) # + lw t3, 4 (a1) # n_threads + sw t3, 4 (t1) # + lw t3, 8 (a1) # base_sp + sw t3, 8 (t1) # + lw t3, 12(a1) # func_ptr + sw t3, 12(t1) # + lw t3, 16(a1) # args + sw t3, 16(t1) # + lw t3, 20(a1) # assigned_warp + sw t3, 20(t1) # + addi t4, t4, 1 # end_i++ + li t5, SIZE # size + bne t4, t5, ec # if ((q.end_i + 1) == SIZE) + mv t4, zero +ec: + sw t4, 4 (t0) # end_i + ret + + +.type queue_dequeue, @function +.global queue_dequeue + +queue_dequeue: + mv t0, a0 # loading base address of q + lw t1, 8 (t0) # t1 = num_j + addi t1, t1, -1 # --t1 + sw t1, 8 (t0) # num_j = t1 + addi t1, t0, 20 # t1 = jobs_addr + lw t4, 0 (t0) # t4 = start_i + li t6, SIZE # size + mv t5, t4 # t5 = start_i + addi t5, t5, 1 # t5++ + bne t5, t6, dc # if ((q.start_i + 1) == SIZE) + mv t5, zero +dc: + sw t5, 0(t0) # storing start_i + slli t2, t4, 5 # index * 32 [log(sizeof(job))] + add t1, t1, t2 # jobs + index + lw t3, 0 (t1) # wid + sw t3, 0 (a1) # + lw t3, 4 (t1) # n_threads + sw t3, 4 (a1) # + lw t3, 8 (t1) # base_sp + sw t3, 8 (a1) # + lw t3, 12(t1) # func_ptr + sw t3, 12(a1) # + lw t3, 16(t1) # args + sw t3, 16(a1) # + lw t3, 20(t1) # assigned_warp + sw t3, 20(a1) # + ret + + +.type queue_isFull, @function +.global queue_isFull +queue_isFull: + mv t0, a0 # loading base address of q + lw t1, 8 (t0) # t1 = num_j + mv a0, zero # ret_val = 0 + li t3, SIZE # t3 = SIZE + bne t3, t1, qf # if (num_j == 1) + addi a0, a0, 1 # ret_val = 1; +qf: + ret + + + +.type queue_isEmpty, @function +.global queue_isEmpty +queue_isEmpty: + mv t0, a0 # loading base address of q + lw t1, 8 (t0) # t1 = num_j + mv a0, zero # ret_val = 0 + mv t3, zero # t3 = 0 + bne t3, t1, qe # if (num_j == 0) + addi a0, a0, 1 # ret_val = 1; +qe: + ret + + +.type queue_availableWarps, @function +.global queue_availableWarps +queue_availableWarps: + mv t0, a0 # loading base address of q + lw t1, 12(t0) # t1 = total_warps + lw t2, 16(t0) # t2 = active_warps + sltu a0, t2, t1 + ret diff --git a/rtl/obj_dir/Vvortex b/rtl/obj_dir/Vvortex index 79791de5..a2de6ab0 100755 Binary files a/rtl/obj_dir/Vvortex and b/rtl/obj_dir/Vvortex differ diff --git a/rtl/obj_dir/Vvortex__ALL.a b/rtl/obj_dir/Vvortex__ALL.a index a9070918..9985c74b 100644 Binary files a/rtl/obj_dir/Vvortex__ALL.a and b/rtl/obj_dir/Vvortex__ALL.a differ diff --git a/rtl/obj_dir/Vvortex__verFiles.dat b/rtl/obj_dir/Vvortex__verFiles.dat index 6adb6004..08c18365 100644 --- a/rtl/obj_dir/Vvortex__verFiles.dat +++ b/rtl/obj_dir/Vvortex__verFiles.dat @@ -6,7 +6,7 @@ S 4626 12889079539 1553237386 0 1553237386 0 "VX_d_e_ S 9200 12889063385 1553237914 0 1553237914 0 "VX_decode.v" S 1503 12889079483 1553237629 0 1553237629 0 "VX_define.v" S 3644 12889083963 1553196174 0 1553196174 0 "VX_e_m_reg.v" -S 4844 12889081819 1553241258 0 1553241258 0 "VX_execute.v" +S 4844 12889081819 1553242107 0 1553242107 0 "VX_execute.v" S 1120 12889050060 1553236935 0 1553236935 0 "VX_f_d_reg.v" S 3537 12889047675 1553236929 0 1553236929 0 "VX_fetch.v" S 5020 12889086478 1553236985 0 1553236985 0 "VX_forwarding.v" @@ -15,11 +15,11 @@ S 2606 12889084513 1553234474 0 1553234474 0 "VX_memo S 958 12889070228 1553234503 0 1553234503 0 "VX_register_file.v" S 806 12889086287 1553236964 0 1553236964 0 "VX_writeback.v" S 12863 12889050092 1553237368 0 1553237368 0 "Vortex.v" -T 88166 12889102709 1553241260 0 1553241260 0 "obj_dir/VVortex.cpp" -T 8044 12889102708 1553241260 0 1553241260 0 "obj_dir/VVortex.h" -T 1800 12889102711 1553241260 0 1553241260 0 "obj_dir/VVortex.mk" -T 530 12889102707 1553241260 0 1553241260 0 "obj_dir/VVortex__Syms.cpp" -T 711 12889102706 1553241260 0 1553241260 0 "obj_dir/VVortex__Syms.h" -T 455 12889102712 1553241260 0 1553241260 0 "obj_dir/VVortex__ver.d" -T 0 0 1553241260 0 1553241260 0 "obj_dir/VVortex__verFiles.dat" -T 1159 12889102710 1553241260 0 1553241260 0 "obj_dir/VVortex_classes.mk" +T 88166 12889102709 1553242391 0 1553242391 0 "obj_dir/VVortex.cpp" +T 8044 12889102708 1553242391 0 1553242391 0 "obj_dir/VVortex.h" +T 1800 12889102711 1553242391 0 1553242391 0 "obj_dir/VVortex.mk" +T 530 12889102707 1553242391 0 1553242391 0 "obj_dir/VVortex__Syms.cpp" +T 711 12889102706 1553242391 0 1553242391 0 "obj_dir/VVortex__Syms.h" +T 455 12889102712 1553242391 0 1553242391 0 "obj_dir/VVortex__ver.d" +T 0 0 1553242391 0 1553242391 0 "obj_dir/VVortex__verFiles.dat" +T 1159 12889102710 1553242391 0 1553242391 0 "obj_dir/VVortex_classes.mk" diff --git a/rtl/results.txt b/rtl/results.txt index 76783cfc..88562e2e 100644 --- a/rtl/results.txt +++ b/rtl/results.txt @@ -1,5 +1,5 @@ -**************** ../../src/riscv_tests/rv32ui-p-add.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-add.hex **************** # Dynamic Instructions: 597 # of total cycles: 608 # of forwarding stalls: 0 @@ -8,7 +8,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-addi.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-addi.hex **************** # Dynamic Instructions: 312 # of total cycles: 323 # of forwarding stalls: 0 @@ -17,7 +17,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-and.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-and.hex **************** # Dynamic Instructions: 595 # of total cycles: 606 # of forwarding stalls: 0 @@ -26,7 +26,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-andi.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-andi.hex **************** # Dynamic Instructions: 246 # of total cycles: 257 # of forwarding stalls: 0 @@ -35,7 +35,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-auipc.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-auipc.hex **************** # Dynamic Instructions: 65 # of total cycles: 76 # of forwarding stalls: 0 @@ -44,7 +44,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-beq.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-beq.hex **************** # Dynamic Instructions: 431 # of total cycles: 442 # of forwarding stalls: 0 @@ -53,7 +53,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-bge.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-bge.hex **************** # Dynamic Instructions: 467 # of total cycles: 478 # of forwarding stalls: 0 @@ -62,7 +62,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-bgeu.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-bgeu.hex **************** # Dynamic Instructions: 492 # of total cycles: 503 # of forwarding stalls: 0 @@ -71,7 +71,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-blt.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-blt.hex **************** # Dynamic Instructions: 431 # of total cycles: 442 # of forwarding stalls: 0 @@ -80,7 +80,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-bltu.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-bltu.hex **************** # Dynamic Instructions: 456 # of total cycles: 467 # of forwarding stalls: 0 @@ -89,7 +89,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-bne.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-bne.hex **************** # Dynamic Instructions: 431 # of total cycles: 442 # of forwarding stalls: 0 @@ -98,7 +98,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-jal.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-jal.hex **************** # Dynamic Instructions: 61 # of total cycles: 72 # of forwarding stalls: 0 @@ -107,7 +107,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-jalr.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-jalr.hex **************** # Dynamic Instructions: 138 # of total cycles: 149 # of forwarding stalls: 0 @@ -116,7 +116,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-lb.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-lb.hex **************** # Dynamic Instructions: 331 # of total cycles: 342 # of forwarding stalls: 0 @@ -125,7 +125,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-lbu.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-lbu.hex **************** # Dynamic Instructions: 331 # of total cycles: 342 # of forwarding stalls: 0 @@ -134,7 +134,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-lh.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-lh.hex **************** # Dynamic Instructions: 339 # of total cycles: 350 # of forwarding stalls: 0 @@ -143,7 +143,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-lhu.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-lhu.hex **************** # Dynamic Instructions: 343 # of total cycles: 354 # of forwarding stalls: 0 @@ -152,7 +152,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-lui.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-lui.hex **************** # Dynamic Instructions: 73 # of total cycles: 84 # of forwarding stalls: 0 @@ -161,7 +161,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-lw.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-lw.hex **************** # Dynamic Instructions: 346 # of total cycles: 357 # of forwarding stalls: 0 @@ -170,7 +170,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-or.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-or.hex **************** # Dynamic Instructions: 598 # of total cycles: 609 # of forwarding stalls: 0 @@ -179,7 +179,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-ori.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-ori.hex **************** # Dynamic Instructions: 253 # of total cycles: 264 # of forwarding stalls: 0 @@ -188,7 +188,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-sb.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-sb.hex **************** # Dynamic Instructions: 571 # of total cycles: 582 # of forwarding stalls: 0 @@ -197,7 +197,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-sh.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-sh.hex **************** # Dynamic Instructions: 603 # of total cycles: 614 # of forwarding stalls: 0 @@ -206,7 +206,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-simple.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-simple.hex **************** # Dynamic Instructions: 37 # of total cycles: 48 # of forwarding stalls: 0 @@ -215,7 +215,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-sll.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-sll.hex **************** # Dynamic Instructions: 633 # of total cycles: 644 # of forwarding stalls: 0 @@ -224,7 +224,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-slli.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-slli.hex **************** # Dynamic Instructions: 311 # of total cycles: 322 # of forwarding stalls: 0 @@ -233,7 +233,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-slt.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-slt.hex **************** # Dynamic Instructions: 591 # of total cycles: 602 # of forwarding stalls: 0 @@ -242,7 +242,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-slti.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-slti.hex **************** # Dynamic Instructions: 307 # of total cycles: 318 # of forwarding stalls: 0 @@ -251,7 +251,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-sltiu.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-sltiu.hex **************** # Dynamic Instructions: 307 # of total cycles: 318 # of forwarding stalls: 0 @@ -260,7 +260,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-sltu.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-sltu.hex **************** # Dynamic Instructions: 591 # of total cycles: 602 # of forwarding stalls: 0 @@ -269,7 +269,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-sra.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-sra.hex **************** # Dynamic Instructions: 654 # of total cycles: 665 # of forwarding stalls: 0 @@ -278,7 +278,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-srai.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-srai.hex **************** # Dynamic Instructions: 326 # of total cycles: 337 # of forwarding stalls: 0 @@ -287,7 +287,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-srl.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-srl.hex **************** # Dynamic Instructions: 648 # of total cycles: 659 # of forwarding stalls: 0 @@ -296,7 +296,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-srli.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-srli.hex **************** # Dynamic Instructions: 320 # of total cycles: 331 # of forwarding stalls: 0 @@ -305,7 +305,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-sub.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-sub.hex **************** # Dynamic Instructions: 587 # of total cycles: 598 # of forwarding stalls: 0 @@ -314,7 +314,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-sw.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-sw.hex **************** # Dynamic Instructions: 612 # of total cycles: 623 # of forwarding stalls: 0 @@ -323,7 +323,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-xor.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-xor.hex **************** # Dynamic Instructions: 597 # of total cycles: 608 # of forwarding stalls: 0 @@ -332,7 +332,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32ui-p-xori.hex **************** +**************** ../../emulator/riscv_tests/rv32ui-p-xori.hex **************** # Dynamic Instructions: 255 # of total cycles: 266 # of forwarding stalls: 0 @@ -341,7 +341,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32um-p-div.hex **************** +**************** ../../emulator/riscv_tests/rv32um-p-div.hex **************** # Dynamic Instructions: 112 # of total cycles: 123 # of forwarding stalls: 0 @@ -350,7 +350,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32um-p-divu.hex **************** +**************** ../../emulator/riscv_tests/rv32um-p-divu.hex **************** # Dynamic Instructions: 113 # of total cycles: 124 # of forwarding stalls: 0 @@ -359,7 +359,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32um-p-mul.hex **************** +**************** ../../emulator/riscv_tests/rv32um-p-mul.hex **************** # Dynamic Instructions: 589 # of total cycles: 600 # of forwarding stalls: 0 @@ -368,7 +368,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32um-p-mulh.hex **************** +**************** ../../emulator/riscv_tests/rv32um-p-mulh.hex **************** # Dynamic Instructions: 585 # of total cycles: 596 # of forwarding stalls: 0 @@ -377,7 +377,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32um-p-mulhsu.hex **************** +**************** ../../emulator/riscv_tests/rv32um-p-mulhsu.hex **************** # Dynamic Instructions: 585 # of total cycles: 596 # of forwarding stalls: 0 @@ -386,7 +386,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32um-p-mulhu.hex **************** +**************** ../../emulator/riscv_tests/rv32um-p-mulhu.hex **************** # Dynamic Instructions: 585 # of total cycles: 596 # of forwarding stalls: 0 @@ -395,7 +395,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32um-p-rem.hex **************** +**************** ../../emulator/riscv_tests/rv32um-p-rem.hex **************** # Dynamic Instructions: 112 # of total cycles: 123 # of forwarding stalls: 0 @@ -404,7 +404,7 @@ # time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING -**************** ../../src/riscv_tests/rv32um-p-remu.hex **************** +**************** ../../emulator/riscv_tests/rv32um-p-remu.hex **************** # Dynamic Instructions: 112 # of total cycles: 123 # of forwarding stalls: 0 diff --git a/rtl/test_bench.cpp b/rtl/test_bench.cpp index 90721a63..be70a1f3 100644 --- a/rtl/test_bench.cpp +++ b/rtl/test_bench.cpp @@ -14,52 +14,52 @@ int main(int argc, char **argv) bool passed = true; std::string tests[NUM_TESTS] = { - "../../src/riscv_tests/rv32ui-p-add.hex", - "../../src/riscv_tests/rv32ui-p-addi.hex", - "../../src/riscv_tests/rv32ui-p-and.hex", - "../../src/riscv_tests/rv32ui-p-andi.hex", - "../../src/riscv_tests/rv32ui-p-auipc.hex", - "../../src/riscv_tests/rv32ui-p-beq.hex", - "../../src/riscv_tests/rv32ui-p-bge.hex", - "../../src/riscv_tests/rv32ui-p-bgeu.hex", - "../../src/riscv_tests/rv32ui-p-blt.hex", - "../../src/riscv_tests/rv32ui-p-bltu.hex", - "../../src/riscv_tests/rv32ui-p-bne.hex", - "../../src/riscv_tests/rv32ui-p-jal.hex", - "../../src/riscv_tests/rv32ui-p-jalr.hex", - "../../src/riscv_tests/rv32ui-p-lb.hex", - "../../src/riscv_tests/rv32ui-p-lbu.hex", - "../../src/riscv_tests/rv32ui-p-lh.hex", - "../../src/riscv_tests/rv32ui-p-lhu.hex", - "../../src/riscv_tests/rv32ui-p-lui.hex", - "../../src/riscv_tests/rv32ui-p-lw.hex", - "../../src/riscv_tests/rv32ui-p-or.hex", - "../../src/riscv_tests/rv32ui-p-ori.hex", - "../../src/riscv_tests/rv32ui-p-sb.hex", - "../../src/riscv_tests/rv32ui-p-sh.hex", - "../../src/riscv_tests/rv32ui-p-simple.hex", - "../../src/riscv_tests/rv32ui-p-sll.hex", - "../../src/riscv_tests/rv32ui-p-slli.hex", - "../../src/riscv_tests/rv32ui-p-slt.hex", - "../../src/riscv_tests/rv32ui-p-slti.hex", - "../../src/riscv_tests/rv32ui-p-sltiu.hex", - "../../src/riscv_tests/rv32ui-p-sltu.hex", - "../../src/riscv_tests/rv32ui-p-sra.hex", - "../../src/riscv_tests/rv32ui-p-srai.hex", - "../../src/riscv_tests/rv32ui-p-srl.hex", - "../../src/riscv_tests/rv32ui-p-srli.hex", - "../../src/riscv_tests/rv32ui-p-sub.hex", - "../../src/riscv_tests/rv32ui-p-sw.hex", - "../../src/riscv_tests/rv32ui-p-xor.hex", - "../../src/riscv_tests/rv32ui-p-xori.hex", - "../../src/riscv_tests/rv32um-p-div.hex", - "../../src/riscv_tests/rv32um-p-divu.hex", - "../../src/riscv_tests/rv32um-p-mul.hex", - "../../src/riscv_tests/rv32um-p-mulh.hex", - "../../src/riscv_tests/rv32um-p-mulhsu.hex", - "../../src/riscv_tests/rv32um-p-mulhu.hex", - "../../src/riscv_tests/rv32um-p-rem.hex", - "../../src/riscv_tests/rv32um-p-remu.hex" + "../../emulator/riscv_tests/rv32ui-p-add.hex", + "../../emulator/riscv_tests/rv32ui-p-addi.hex", + "../../emulator/riscv_tests/rv32ui-p-and.hex", + "../../emulator/riscv_tests/rv32ui-p-andi.hex", + "../../emulator/riscv_tests/rv32ui-p-auipc.hex", + "../../emulator/riscv_tests/rv32ui-p-beq.hex", + "../../emulator/riscv_tests/rv32ui-p-bge.hex", + "../../emulator/riscv_tests/rv32ui-p-bgeu.hex", + "../../emulator/riscv_tests/rv32ui-p-blt.hex", + "../../emulator/riscv_tests/rv32ui-p-bltu.hex", + "../../emulator/riscv_tests/rv32ui-p-bne.hex", + "../../emulator/riscv_tests/rv32ui-p-jal.hex", + "../../emulator/riscv_tests/rv32ui-p-jalr.hex", + "../../emulator/riscv_tests/rv32ui-p-lb.hex", + "../../emulator/riscv_tests/rv32ui-p-lbu.hex", + "../../emulator/riscv_tests/rv32ui-p-lh.hex", + "../../emulator/riscv_tests/rv32ui-p-lhu.hex", + "../../emulator/riscv_tests/rv32ui-p-lui.hex", + "../../emulator/riscv_tests/rv32ui-p-lw.hex", + "../../emulator/riscv_tests/rv32ui-p-or.hex", + "../../emulator/riscv_tests/rv32ui-p-ori.hex", + "../../emulator/riscv_tests/rv32ui-p-sb.hex", + "../../emulator/riscv_tests/rv32ui-p-sh.hex", + "../../emulator/riscv_tests/rv32ui-p-simple.hex", + "../../emulator/riscv_tests/rv32ui-p-sll.hex", + "../../emulator/riscv_tests/rv32ui-p-slli.hex", + "../../emulator/riscv_tests/rv32ui-p-slt.hex", + "../../emulator/riscv_tests/rv32ui-p-slti.hex", + "../../emulator/riscv_tests/rv32ui-p-sltiu.hex", + "../../emulator/riscv_tests/rv32ui-p-sltu.hex", + "../../emulator/riscv_tests/rv32ui-p-sra.hex", + "../../emulator/riscv_tests/rv32ui-p-srai.hex", + "../../emulator/riscv_tests/rv32ui-p-srl.hex", + "../../emulator/riscv_tests/rv32ui-p-srli.hex", + "../../emulator/riscv_tests/rv32ui-p-sub.hex", + "../../emulator/riscv_tests/rv32ui-p-sw.hex", + "../../emulator/riscv_tests/rv32ui-p-xor.hex", + "../../emulator/riscv_tests/rv32ui-p-xori.hex", + "../../emulator/riscv_tests/rv32um-p-div.hex", + "../../emulator/riscv_tests/rv32um-p-divu.hex", + "../../emulator/riscv_tests/rv32um-p-mul.hex", + "../../emulator/riscv_tests/rv32um-p-mulh.hex", + "../../emulator/riscv_tests/rv32um-p-mulhsu.hex", + "../../emulator/riscv_tests/rv32um-p-mulhu.hex", + "../../emulator/riscv_tests/rv32um-p-rem.hex", + "../../emulator/riscv_tests/rv32um-p-remu.hex" }; for (int ii = 0; ii < NUM_TESTS; ii++) diff --git a/src/test_riscv.sh b/src/test_riscv.sh deleted file mode 100755 index 8ae14373..00000000 --- a/src/test_riscv.sh +++ /dev/null @@ -1,4 +0,0 @@ -echo start > results.txt - -echo ./vortex_software/vortex_test.hex -./harptool -E -a rv32i --core ./vortex_software/vortex_test.hex -s -b diff --git a/util/Makefile b/util/Makefile deleted file mode 100644 index dda0940b..00000000 --- a/util/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -bin2mif : bin2mif.cpp - -clean : - rm -f bin2mif diff --git a/util/bin2mif.cpp b/util/bin2mif.cpp deleted file mode 100644 index 9884daf8..00000000 --- a/util/bin2mif.cpp +++ /dev/null @@ -1,64 +0,0 @@ -// bin2mif -- Convert binary file to Memory Initialization File used by some -// FPGA toolchains. - -#include -#include -#include -#include -#include - -int main(int argc, char** argv) { - using namespace std; - - if (argc != 5) { - cerr << "Usage:\n " << argv[0] << ' ' << "" - << " \n";; - return 1; - } - - ifstream in(argv[3]); - ofstream out(argv[4]); - - if (!in) { - cerr << "Failed to open input file \"" << argv[3] << "\"\n"; - return 1; - } - - if (!out) { - cerr << "Failed to open output file \"" << argv[4] << "\"\n"; - return 1; - } - - unsigned word(atol(argv[1])), mem_sz(atol(argv[2])/word); - - out << "DEPTH = " << mem_sz << ";\n" - << "WIDTH = " << word*8 << ";\n" - << "ADDRESS_RADIX = HEX;\n" - << "DATA_RADIX = HEX;\n" - << "CONTENT\n" - << "BEGIN\n"; - - // HARP is little endian, so no matter what the endianness of the machine on - // which this utility runs, this swapping of the byte order when constructing - // hex values is necessary. - for (unsigned j = 0; j < mem_sz; ++j) { - stack bytes; - - out << setw(4) << setfill('0') << hex << j << " : "; - for (unsigned i = 0; i < word; ++i) { - bytes.push(in.get()); - if (in.eof()) { bytes.pop(); while(i++ < word) bytes.push(0); } - } - - for (unsigned i = 0; i < word; ++i) { - out << hex << setw(2) << setfill('0') << unsigned(bytes.top()); - bytes.pop(); - } - out << ";\n"; - if (in.eof()) break; - } - - out << "END;\n"; - - return 0; -}