pipeline refactoring - fmax >= 222 mhz

hw/rtl/libs/VX_onehot_encooder.v

@@ -7,12 +7,10 @@ module VX_onehot_encoder #(
     output reg [`LOG2UP(N)-1:0] binary,
     output reg valid
 );
-    integer i;
-
     always @(*) begin
         valid = 1'b0;    
         binary = `LOG2UP(N)'(0);                
-        for (i = 0; i < N; i++) begin
+        for (integer i = 0; i < N; i++) begin
             if (onehot[i]) begin
                 valid = 1'b1;
                 binary = `LOG2UP(N)'(i);