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pipeline refactoring - fmax >= 222 mhz

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Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
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18
hw/rtl/libs/VX_multiplier.v
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@@ -50,18 +50,18 @@ module VX_multiplier #(
reg [WIDTHP-1:0] result_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE; i++) begin
for (genvar i = 0; i < PIPELINE; i++) begin
always @(posedge clk) begin
if (reset) begin
result_pipe[i] <= 0;
end
else if (clk_en) begin
if (i == 0) begin
result_pipe[i] <= result_unqual;
end else begin
result_pipe[i] <= result_pipe[i-1];
end
end else begin
if (clk_en) begin
if (i == 0) begin
result_pipe[i] <= result_unqual;
end else begin
result_pipe[i] <= result_pipe[i-1];
end
end
end
end
end