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pipeline refactoring - fmax >= 222 mhz

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This commit is contained in:
Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
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15
hw/rtl/libs/VX_matrix_arbiter.v
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@@ -24,11 +24,9 @@ module VX_matrix_arbiter #(
reg [N-1:1] state [0:N-1];
wire [N-1:0] pri [0:N-1];
genvar i, j;
for (i = 0; i < N; i++) begin
for (j = 0; j < N; j++) begin
for (genvar i = 0; i < N; i++) begin
for (genvar j = 0; j < N; j++) begin
if (j > i) begin
assign pri[j][i] = requests[i] && state[i][j];
end
@@ -43,13 +41,12 @@ module VX_matrix_arbiter #(
assign grant_onehot[i] = requests[i] && !(| pri[i]);
end
for (i = 0; i < N; i++) begin
for (j = i + 1; j < N; j++) begin
for (genvar i = 0; i < N; i++) begin
for (genvar j = i + 1; j < N; j++) begin
always @(posedge clk) begin
if (reset) begin
state[i][j] <= 0;
end
else begin
end else begin
state[i][j] <= (state[i][j] || grant_onehot[j]) && !grant_onehot[i];
end
end