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pipeline refactoring - fmax >= 222 mhz

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This commit is contained in:
Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
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18
hw/rtl/libs/VX_cam_buffer.v
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@@ -32,19 +32,17 @@ module VX_cam_buffer #(
.valid_out (free_valid)
);
integer i;
always @(*) begin
free_slots_n = free_slots;
if (acquire_slot) begin
free_slots_n[write_addr_r] = 0;
end
for (i = 0; i < RPORTS; i++) begin
for (integer i = 0; i < RPORTS; i++) begin
if (release_slot[i]) begin
free_slots_n[read_addr[i]] = 1;
end
read_data[i] = entries[read_addr[i]];
end
end
if (acquire_slot) begin
free_slots_n[write_addr_r] = 0;
end
end
always @(posedge clk) begin
@@ -54,12 +52,12 @@ module VX_cam_buffer #(
write_addr_r <= ADDRW'(1'b0);
end else begin
if (acquire_slot) begin
assert(1 == free_slots[write_addr]);
assert(1 == free_slots[write_addr]) else $display("%t: inused slot at port %d", $time, write_addr);
entries[write_addr] <= write_data;
end
for (i = 0; i < RPORTS; i++) begin
for (integer i = 0; i < RPORTS; i++) begin
if (release_slot[i]) begin
assert(0 == free_slots[read_addr[i]]);
assert(0 == free_slots[read_addr[i]]) else $display("%t: freed slot at port %d", $time, read_addr[i]);
end
end
free_slots <= free_slots_n;

4
hw/rtl/libs/VX_countones.v
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@@ -7,11 +7,9 @@ module VX_countones #(
input wire [N-1:0] valids,
output reg [$clog2(N):0] count
);
integer i;
always @(*) begin
count = 0;
for (i = N-1; i >= 0; i = i - 1) begin
for (integer i = N-1; i >= 0; i = i - 1) begin
if (valids[i]) begin
count = count + 1;
end

31
hw/rtl/libs/VX_divide.v
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@@ -52,15 +52,6 @@ module VX_divide #(
reg [WIDTHD-1:0] remainder_unqual;
always @(*) begin
`ifndef SYNTHESIS
// this edge case kills verilator in some cases by causing a division
// overflow exception. INT_MIN / -1 (on x86)
if (numer == {1'b1, (WIDTHN-1)'(1'b0)}
&& denom == {WIDTHD{1'b1}}) begin
quotient_unqual = 0;
remainder_unqual = 0;
end else
`endif
begin
if (NSIGNED && DSIGNED) begin
quotient_unqual = $signed(numer) / $signed(denom);
@@ -88,21 +79,21 @@ module VX_divide #(
reg [WIDTHN-1:0] quotient_pipe [0:PIPELINE-1];
reg [WIDTHD-1:0] remainder_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE; i++) begin
for (genvar i = 0; i < PIPELINE; i++) begin
always @(posedge clk) begin
if (reset) begin
quotient_pipe[i] <= 0;
remainder_pipe[i] <= 0;
end
else if (clk_en) begin
if (i == 0) begin
quotient_pipe[i] <= quotient_unqual;
remainder_pipe[i] <= remainder_unqual;
end else begin
quotient_pipe[i] <= quotient_pipe[i-1];
remainder_pipe[i] <= remainder_pipe[i-1];
end
end else begin
if (clk_en) begin
if (i == 0) begin
quotient_pipe[i] <= quotient_unqual;
remainder_pipe[i] <= remainder_unqual;
end else begin
quotient_pipe[i] <= quotient_pipe[i-1];
remainder_pipe[i] <= remainder_pipe[i-1];
end
end
end
end
end

64
hw/rtl/libs/VX_elastic_buffer.v
View File

@@ -14,25 +14,53 @@ module VX_elastic_buffer #(
input wire ready_out,
output wire valid_out
);
wire empty, full;
if (0 == SIZE) begin
VX_generic_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED)
) queue (
.clk (clk),
.reset (reset),
.push (valid_in),
.pop (ready_out),
.data_in(data_in),
.data_out(data_out),
.empty (empty),
.full (full),
`UNUSED_PIN (size)
);
reg [DATAW-1:0] skid_buffer;
reg skid_valid;
assign ready_in = ~full;
assign valid_out = ~empty;
always @(posedge clk) begin
if (reset) begin
skid_valid <= 0;
end else begin
if (valid_in && ~ready_out) begin
assert(~skid_valid);
skid_buffer <= data_in;
skid_valid <= 1;
end
if (ready_out) begin
skid_valid <= 0;
end
end
end
assign ready_in = ready_out || ~skid_valid;
assign data_out = skid_valid ? skid_buffer : data_in;
assign valid_out = valid_in || skid_valid;
end else begin
wire empty, full;
VX_generic_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED)
) queue (
.clk (clk),
.reset (reset),
.push (valid_in),
.pop (ready_out),
.data_in(data_in),
.data_out(data_out),
.empty (empty),
.full (full),
`UNUSED_PIN (size)
);
assign ready_in = ~full;
assign valid_out = ~empty;
end
endmodule

12
hw/rtl/libs/VX_fair_arbiter.v
View File

@@ -11,7 +11,7 @@ module VX_fair_arbiter #(
output wire grant_valid
);
if (N == 1) begin
if (N == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
@@ -33,11 +33,13 @@ module VX_fair_arbiter #(
if (reset) begin
requests_use <= 0;
refill_original <= 0;
end else if (refill) begin
requests_use <= refill_value;
refill_original <= refill_value;
end else begin
requests_use <= update_value;
if (refill) begin
requests_use <= refill_value;
refill_original <= refill_value;
end else begin
requests_use <= update_value;
end
end
end

3
hw/rtl/libs/VX_generic_queue.v
View File

@@ -38,7 +38,6 @@ module VX_generic_queue #(
end else if (reading && !writing) begin
size_r <= 0;
end
if (writing) begin
head_r <= data_in;
end
@@ -146,7 +145,7 @@ module VX_generic_queue #(
end
bypass_r <= writing
&& (empty_r || ((1 == size_r) && reading)); // empty or about to go empty
&& (empty_r || ((1 == size_r) && reading)); // empty or about to go empty
curr_r <= data_in;
head_r <= data[reading ? rd_ptr_next_r : rd_ptr_r];

15
hw/rtl/libs/VX_matrix_arbiter.v
View File

@@ -24,11 +24,9 @@ module VX_matrix_arbiter #(
reg [N-1:1] state [0:N-1];
wire [N-1:0] pri [0:N-1];
genvar i, j;
for (i = 0; i < N; i++) begin
for (j = 0; j < N; j++) begin
for (genvar i = 0; i < N; i++) begin
for (genvar j = 0; j < N; j++) begin
if (j > i) begin
assign pri[j][i] = requests[i] && state[i][j];
end
@@ -43,13 +41,12 @@ module VX_matrix_arbiter #(
assign grant_onehot[i] = requests[i] && !(| pri[i]);
end
for (i = 0; i < N; i++) begin
for (j = i + 1; j < N; j++) begin
for (genvar i = 0; i < N; i++) begin
for (genvar j = i + 1; j < N; j++) begin
always @(posedge clk) begin
if (reset) begin
state[i][j] <= 0;
end
else begin
end else begin
state[i][j] <= (state[i][j] || grant_onehot[j]) && !grant_onehot[i];
end
end

18
hw/rtl/libs/VX_multiplier.v
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@@ -50,18 +50,18 @@ module VX_multiplier #(
reg [WIDTHP-1:0] result_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE; i++) begin
for (genvar i = 0; i < PIPELINE; i++) begin
always @(posedge clk) begin
if (reset) begin
result_pipe[i] <= 0;
end
else if (clk_en) begin
if (i == 0) begin
result_pipe[i] <= result_unqual;
end else begin
result_pipe[i] <= result_pipe[i-1];
end
end else begin
if (clk_en) begin
if (i == 0) begin
result_pipe[i] <= result_unqual;
end else begin
result_pipe[i] <= result_pipe[i-1];
end
end
end
end
end

4
hw/rtl/libs/VX_onehot_encooder.v
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@@ -7,12 +7,10 @@ module VX_onehot_encoder #(
output reg [`LOG2UP(N)-1:0] binary,
output reg valid
);
integer i;
always @(*) begin
valid = 1'b0;
binary = `LOG2UP(N)'(0);
for (i = 0; i < N; i++) begin
for (integer i = 0; i < N; i++) begin
if (onehot[i]) begin
valid = 1'b1;
binary = `LOG2UP(N)'(i);

6
hw/rtl/libs/VX_priority_encoder.v
View File

@@ -6,13 +6,11 @@ module VX_priority_encoder #(
input wire [N-1:0] data_in,
output reg [`LOG2UP(N)-1:0] data_out,
output reg valid_out
);
integer i;
);
always @(*) begin
data_out = 0;
valid_out = 0;
for (i = N-1; i >= 0; i = i - 1) begin
for (integer i = N-1; i >= 0; i = i - 1) begin
if (data_in[i]) begin
data_out = `LOG2UP(N)'(i);
valid_out = 1;

9
hw/rtl/libs/VX_rr_arbiter.v
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@@ -26,12 +26,10 @@ module VX_rr_arbiter #(
reg [`CLOG2(N)-1:0] state;
reg [N-1:0] grant_onehot_r;
integer i, j;
always @(*) begin
for (i = 0; i < N; i++) begin
for (integer i = 0; i < N; i++) begin
grant_table[i] = `CLOG2(N)'(i);
for (j = 0; j < N; j++) begin
for (integer j = 0; j < N; j++) begin
if (requests[(i+j) % N]) begin
grant_table[i] = `CLOG2(N)'((i+j) % N);
end
@@ -44,8 +42,7 @@ module VX_rr_arbiter #(
always @(posedge clk) begin
if (reset) begin
state <= 0;
end
else begin
end else begin
state <= grant_index;
end
end

1
hw/rtl/libs/VX_scope.v
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@@ -74,7 +74,6 @@ module VX_scope #(
read_delta <= 0;
data_valid <= 0;
end else begin
if (bus_write) begin
case (cmd_type)
CMD_GET_VALID,

4
hw/rtl/libs/VX_shift_register.v
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@@ -16,7 +16,7 @@ module VX_shift_register #(
always @(posedge clk) begin
if (reset) begin
entries <= '0;
entries <= (DEPTH * DATAW)'(0);
end else begin
if (enable) begin
entries <= in;
@@ -28,7 +28,7 @@ module VX_shift_register #(
always @(posedge clk) begin
if (reset) begin
entries <= '0;
entries <= (DEPTH * DATAW)'(0);
end else begin
if (enable) begin
entries <= {entries[DEPTH-2:0], in};