pipeline refactoring - fmax >= 222 mhz

hw/rtl/interfaces/VX_alu_req_if.v

@@ -7,18 +7,22 @@ interface VX_alu_req_if ();
 
     wire                    valid;    
     wire [`ISTAG_BITS-1:0]  issue_tag;
+`DEBUG_BEGIN
+    wire [`NW_BITS-1:0]     wid;    
     wire [`NUM_THREADS-1:0] thread_mask;
-    wire [`NW_BITS-1:0]     warp_num;
+`DEBUG_END        
     wire [31:0]             curr_PC;
 
-    wire [`ALU_BITS-1:0]    alu_op;
+    wire [`ALU_BITS-1:0]    op;
+
+    wire                    rs1_is_PC;
+    wire                    rs2_is_imm;
+
+    wire [31:0]             imm;
 
     wire [`NUM_THREADS-1:0][31:0] rs1_data;
     wire [`NUM_THREADS-1:0][31:0] rs2_data;
     
-    wire [31:0]             offset;
-    wire [31:0]             next_PC;    
-    
     wire                    ready;
 
 endinterface