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pipeline refactoring - fmax >= 222 mhz

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This commit is contained in:
Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
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6
hw/rtl/VX_csr_io_arb.v
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@@ -51,9 +51,7 @@ module VX_csr_io_arb #(
end else begin
genvar i;
for (i = 0; i < NUM_REQUESTS; i++) begin
for (genvar i = 0; i < NUM_REQUESTS; i++) begin
assign out_csr_io_req_valid[i] = in_csr_io_req_valid && (request_id == `REQS_BITS'(i));
assign out_csr_io_req_rw[i] = in_csr_io_req_rw;
assign out_csr_io_req_addr[i] = in_csr_io_req_addr;
@@ -78,7 +76,7 @@ module VX_csr_io_arb #(
assign out_csr_io_rsp_valid = in_csr_io_rsp_valid [bus_rsp_sel];
assign out_csr_io_rsp_data = in_csr_io_rsp_data [bus_rsp_sel];
for (i = 0; i < NUM_REQUESTS; i++) begin
for (genvar i = 0; i < NUM_REQUESTS; i++) begin
assign in_csr_io_rsp_ready[i] = out_csr_io_rsp_ready && (bus_rsp_sel == `REQS_BITS'(i));
end