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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-03 17:10:02 -04:00
parent a1dc90b951
commit 69f607b73e
83 changed files with 30487 additions and 30536 deletions
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138
hw/rtl/Vortex_Socket.v
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@@ -6,10 +6,6 @@ module Vortex_Socket (
input wire clk,
input wire reset,
// IO
output wire io_valid[(`NUM_CORES * `NUM_CLUSTERS)-1:0],
output wire[31:0] io_data [(`NUM_CORES * `NUM_CLUSTERS)-1:0],
// DRAM Req
output wire dram_req_read,
output wire dram_req_write,
@@ -24,32 +20,26 @@ module Vortex_Socket (
input wire[`L3DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// LLC Snooping
// Cache Snooping
input wire llc_snp_req_valid,
input wire[`L3DRAM_ADDR_WIDTH-1:0] llc_snp_req_addr,
output wire llc_snp_req_ready,
// I/O
output wire io_valid,
output wire [31:0] io_data,
input wire io_ready,
// Debug
output wire ebreak
);
if (`NUM_CLUSTERS == 1) begin
wire[`NUM_CORES-1:0] cluster_io_valid;
wire[`NUM_CORES-1:0][31:0] cluster_io_data;
genvar i;
for (i = 0; i < `NUM_CORES; i=i+1) begin
assign io_valid [i] = cluster_io_valid [i];
assign io_data [i] = cluster_io_data [i];
end
Vortex_Cluster #(
.CLUSTER_ID(0)
) Vortex_Cluster (
.clk (clk),
.reset (reset),
.io_valid (cluster_io_valid),
.io_data (cluster_io_data),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
@@ -67,51 +57,46 @@ module Vortex_Socket (
.llc_snp_req_addr (llc_snp_req_addr),
.llc_snp_req_ready (llc_snp_req_ready),
.io_valid (io_valid),
.io_data (io_data),
.io_ready (io_ready),
.ebreak (ebreak)
);
end else begin
wire snp_fwd_valid;
wire[`L3DRAM_ADDR_WIDTH-1:0] snp_fwd_addr;
wire[`NUM_CLUSTERS-1:0] per_cluster_snp_fwd_ready;
wire[`NUM_CLUSTERS-1:0] per_cluster_ebreak;
assign ebreak = (& per_cluster_ebreak);
// // DRAM Dcache Req
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_write;
// DRAM Dcache Req
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_read;
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_write;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data_up;
wire l3_core_req_ready;
// // DRAM Dcache Rsp
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready;
// DRAM Dcache Rsp
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid;
wire[`NUM_CLUSTERS-1:0][`L3DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data;
wire[`NUM_CLUSTERS-1:0][`L3DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag;
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready;
wire[`NUM_CLUSTERS-1:0][`L3DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data_up;
wire snp_fwd_valid;
wire[`L3DRAM_ADDR_WIDTH-1:0] snp_fwd_addr;
wire[`NUM_CLUSTERS-1:0] per_cluster_snp_fwd_ready;
wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0] per_cluster_io_valid;
wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0][31:0] per_cluster_io_data;
`IGNORE_WARNINGS_BEGIN
wire[`NUM_CLUSTERS-1:0] per_cluster_io_valid;
wire[`NUM_CLUSTERS-1:0][31:0] per_cluster_io_data;
`IGNORE_WARNINGS_END
genvar i, j;
for (i = 0; i < `NUM_CLUSTERS; i = i + 1) begin
for (j = 0; j < `NUM_CORES; j = j + 1) begin
assign io_valid[j+(i*`NUM_CORES)] = per_cluster_io_valid[i][j];
assign io_data[j+(i*`NUM_CORES)] = per_cluster_io_data[i][j];
end
assign per_cluster_dram_req_data[i] = per_cluster_dram_req_data_up[i];
assign per_cluster_dram_rsp_data_up[i] = per_cluster_dram_rsp_data[i];
end
wire[`NUM_CLUSTERS-1:0] per_cluster_ebreak;
assign io_valid = per_cluster_io_valid[0];
assign io_data = per_cluster_io_data[0];
assign ebreak = (& per_cluster_ebreak);
genvar i;
for (i = 0; i < `NUM_CLUSTERS; i=i+1) begin
Vortex_Cluster #(
.CLUSTER_ID(i)
@@ -119,34 +104,35 @@ module Vortex_Socket (
.clk (clk),
.reset (reset),
.io_valid (per_cluster_io_valid [i]),
.io_data (per_cluster_io_data [i]),
.dram_req_write (per_cluster_dram_req_write [i]),
.dram_req_read (per_cluster_dram_req_read [i]),
.dram_req_addr (per_cluster_dram_req_addr [i]),
.dram_req_data (per_cluster_dram_req_data_up [i]),
.dram_req_tag (per_cluster_dram_req_tag [i]),
.dram_req_write (per_cluster_dram_req_write [i]),
.dram_req_read (per_cluster_dram_req_read [i]),
.dram_req_addr (per_cluster_dram_req_addr [i]),
.dram_req_data (per_cluster_dram_req_data [i]),
.dram_req_tag (per_cluster_dram_req_tag [i]),
.dram_req_ready (l3_core_req_ready),
.dram_rsp_valid (per_cluster_dram_rsp_valid [i]),
.dram_rsp_data (per_cluster_dram_rsp_data_up [i]),
.dram_rsp_tag (per_cluster_dram_rsp_tag [i]),
.dram_rsp_ready (per_cluster_dram_rsp_ready [i]),
.dram_rsp_valid (per_cluster_dram_rsp_valid [i]),
.dram_rsp_data (per_cluster_dram_rsp_data [i]),
.dram_rsp_tag (per_cluster_dram_rsp_tag [i]),
.dram_rsp_ready (per_cluster_dram_rsp_ready [i]),
.llc_snp_req_valid (snp_fwd_valid),
.llc_snp_req_addr (snp_fwd_addr),
.llc_snp_req_ready (per_cluster_snp_fwd_ready [i]),
.llc_snp_req_ready (per_cluster_snp_fwd_ready [i]),
.ebreak (per_cluster_ebreak [i])
.io_valid (per_cluster_io_valid [i]),
.io_data (per_cluster_io_data [i]),
.io_ready (io_ready),
.ebreak (per_cluster_ebreak [i])
);
end
// L3 Cache ///////////////////////////////////////////////////////////
wire[`L3NUM_REQUESTS-1:0] l3_core_req_valid;
wire[`L3NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l3_core_req_mem_write;
wire[`L3NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l3_core_req_mem_read;
wire[`L3NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l3_core_req_read;
wire[`L3NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l3_core_req_write;
wire[`L3NUM_REQUESTS-1:0][31:0] l3_core_req_addr;
wire[`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data;
wire[`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag;
@@ -156,23 +142,17 @@ module Vortex_Socket (
wire[`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag;
wire[`L3NUM_REQUESTS-1:0] l3_core_rsp_ready;
wire[`L3DRAM_LINE_WIDTH-1:0] l3_dram_req_data;
wire[`L3DRAM_LINE_WIDTH-1:0] l3_dram_rsp_data;
assign dram_req_data = l3_dram_req_data;
assign l3_dram_rsp_data = dram_rsp_data;
for (i = 0; i < `L3NUM_REQUESTS; i=i+1) begin
// Core Request
assign l3_core_req_valid [i] = (per_cluster_dram_req_read[i] | per_cluster_dram_req_write[i]);
assign l3_core_req_mem_read [i] = per_cluster_dram_req_read [i] ? `WORD_SEL_LW : `WORD_SEL_NO;
assign l3_core_req_mem_write [i] = per_cluster_dram_req_write[i] ? `WORD_SEL_LW : `WORD_SEL_NO;
assign l3_core_req_addr [i] = {per_cluster_dram_req_addr [i], {`LOG2UP(`L2BANK_LINE_SIZE){1'b0}}};
assign l3_core_req_tag [i] = per_cluster_dram_req_tag [i];
assign l3_core_req_data [i] = per_cluster_dram_req_data [i];
assign l3_core_req_valid [i] = (per_cluster_dram_req_read [i] | per_cluster_dram_req_write [i]);
assign l3_core_req_read [i] = per_cluster_dram_req_read [i] ? `WORD_SEL_LW : `WORD_SEL_NO;
assign l3_core_req_write [i] = per_cluster_dram_req_write [i] ? `WORD_SEL_LW : `WORD_SEL_NO;
assign l3_core_req_addr [i] = {per_cluster_dram_req_addr [i], {`LOG2UP(`L2BANK_LINE_SIZE){1'b0}}};
assign l3_core_req_tag [i] = per_cluster_dram_req_tag [i];
assign l3_core_req_data [i] = per_cluster_dram_req_data [i];
// Core can't accept Response
assign l3_core_rsp_ready [i] = per_cluster_dram_rsp_ready[i];
// Core Response
assign l3_core_rsp_ready [i] = per_cluster_dram_rsp_ready[i];
// Cache Fill Response
assign per_cluster_dram_rsp_valid [i] = l3_core_rsp_valid [i];
@@ -208,8 +188,8 @@ module Vortex_Socket (
// Core request
.core_req_valid (l3_core_req_valid),
.core_req_read (l3_core_req_mem_read),
.core_req_write (l3_core_req_mem_write),
.core_req_read (l3_core_req_read),
.core_req_write (l3_core_req_write),
.core_req_addr (l3_core_req_addr),
.core_req_data (l3_core_req_data),
.core_req_tag (l3_core_req_tag),
@@ -219,19 +199,19 @@ module Vortex_Socket (
.core_rsp_valid (l3_core_rsp_valid),
.core_rsp_data (l3_core_rsp_data),
.core_rsp_tag (l3_core_rsp_tag),
.core_rsp_ready (|l3_core_rsp_ready),
.core_rsp_ready (& l3_core_rsp_ready),
// DRAM request
.dram_req_write (dram_req_write),
.dram_req_read (dram_req_read),
.dram_req_addr (dram_req_addr),
.dram_req_data (l3_dram_req_data),
.dram_req_data (dram_req_data),
.dram_req_tag (dram_req_tag),
.dram_req_ready (dram_req_ready),
// DRAM response
.dram_rsp_valid (dram_rsp_valid),
.dram_rsp_data (l3_dram_rsp_data),
.dram_rsp_data (dram_rsp_data),
.dram_rsp_tag (dram_rsp_tag),
.dram_rsp_ready (dram_rsp_ready),