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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-03 17:10:02 -04:00
parent a1dc90b951
commit 69f607b73e
83 changed files with 30487 additions and 30536 deletions
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13
hw/rtl/VX_define.vh
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@@ -50,17 +50,6 @@
`define CSR_WIDTH 12
///////////////////////////////////////////////////////////////////////////////
`define CSR_THREAD 12'h020
`define CSR_WARP 12'h021
`define CSR_WARP_ID 12'h022
`define CSR_CYCL_L 12'hC00;
`define CSR_CYCL_H 12'hC80;
`define CSR_INST_L 12'hC02;
`define CSR_INST_H 12'hC82;
///////////////////////////////////////////////////////////////////////////////
`define R_INST 7'd51
@@ -192,7 +181,7 @@
`define L2DRAM_ADDR_WIDTH (32 - `CLOG2(`L2BANK_LINE_SIZE))
// DRAM request tag bits
`define L2DRAM_TAG_WIDTH ((`NUM_CORES > 1) ? `L2DRAM_ADDR_WIDTH : (`L2DRAM_ADDR_WIDTH+1))
`define L2DRAM_TAG_WIDTH (`L2_ENABLE ? `L2DRAM_ADDR_WIDTH : (`L2DRAM_ADDR_WIDTH+`CLOG2(`NUM_CORES*2)))
////////////////////////// L3cache Configurable Knobs /////////////////////////