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Added HW threads - Infinite loop + fixed valid

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This commit is contained in:
felsabbagh3
2019-03-27 03:53:59 -04:00
parent 9b42e79dcf
commit 68f3ba84e5
17 changed files with 623 additions and 224 deletions
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8
rtl/VX_d_e_reg.v
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@@ -26,7 +26,7 @@ module VX_d_e_reg (
input wire in_jal, input wire in_jal,
input wire[31:0] in_jal_offset, input wire[31:0] in_jal_offset,
input wire in_freeze, input wire in_freeze,
input wire[`NT_M1:0] in_valid, input wire in_valid[`NT_M1:0],
output wire[11:0] out_csr_address, // done output wire[11:0] out_csr_address, // done
output wire out_is_csr, // done output wire out_is_csr, // done
@@ -47,7 +47,7 @@ module VX_d_e_reg (
output wire out_jal, output wire out_jal,
output wire[31:0] out_jal_offset, output wire[31:0] out_jal_offset,
output wire[31:0] out_PC_next, output wire[31:0] out_PC_next,
output wire[`NT_M1:0] out_valid output wire out_valid[`NT_M1:0]
); );
@@ -70,10 +70,10 @@ module VX_d_e_reg (
reg[31:0] curr_PC; reg[31:0] curr_PC;
reg jal; reg jal;
reg[31:0] jal_offset; reg[31:0] jal_offset;
reg[`NT_M1:0] valid; reg valid[`NT_M1:0];
reg[31:0] reg_data_z[`NT_T2_M1:0]; reg[31:0] reg_data_z[`NT_T2_M1:0];
reg[`NT_M1:0] valid_z; reg valid_z[`NT_M1:0];
integer ini_reg; integer ini_reg;
initial begin initial begin

6
rtl/VX_decode.v
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@@ -6,12 +6,12 @@ module VX_decode(
input wire clk, input wire clk,
input wire[31:0] in_instruction, input wire[31:0] in_instruction,
input wire[31:0] in_curr_PC, input wire[31:0] in_curr_PC,
input wire[`NT_M1:0] in_valid, input wire in_valid[`NT_M1:0],
// WriteBack inputs // WriteBack inputs
input wire[31:0] in_write_data[`NT_M1:0], input wire[31:0] in_write_data[`NT_M1:0],
input wire[4:0] in_rd, input wire[4:0] in_rd,
input wire[1:0] in_wb, input wire[1:0] in_wb,
input wire[`NT_M1:0] in_wb_valid, input wire in_wb_valid[`NT_M1:0],
// FORWARDING INPUTS // FORWARDING INPUTS
input wire in_src1_fwd, input wire in_src1_fwd,
@@ -40,7 +40,7 @@ module VX_decode(
output reg[31:0] out_jal_offset, output reg[31:0] out_jal_offset,
output reg[19:0] out_upper_immed, output reg[19:0] out_upper_immed,
output wire[31:0] out_PC_next, output wire[31:0] out_PC_next,
output wire[`NT_M1:0] out_valid output wire out_valid[`NT_M1:0]
); );
wire[6:0] curr_opcode; wire[6:0] curr_opcode;

6
rtl/VX_e_m_reg.v
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@@ -23,7 +23,7 @@ module VX_e_m_reg (
input wire in_jal, input wire in_jal,
input wire[31:0] in_jal_dest, input wire[31:0] in_jal_dest,
input wire in_freeze, input wire in_freeze,
input wire[`NT_M1:0] in_valid, input wire in_valid[`NT_M1:0],
output wire[11:0] out_csr_address, output wire[11:0] out_csr_address,
output wire out_is_csr, output wire out_is_csr,
@@ -42,7 +42,7 @@ module VX_e_m_reg (
output wire out_jal, output wire out_jal,
output wire[31:0] out_jal_dest, output wire[31:0] out_jal_dest,
output wire[31:0] out_PC_next, output wire[31:0] out_PC_next,
output wire[`NT_M1:0] out_valid output wire out_valid[`NT_M1:0]
); );
@@ -63,7 +63,7 @@ module VX_e_m_reg (
reg[2:0] branch_type; reg[2:0] branch_type;
reg jal; reg jal;
reg[31:0] jal_dest; reg[31:0] jal_dest;
reg[`NT_M1:0] valid; reg valid[`NT_M1:0];
// reg[31:0] reg_data_z[`NT_T2_M1:0]; // reg[31:0] reg_data_z[`NT_T2_M1:0];
// reg[`NT_M1:0] valid_z; // reg[`NT_M1:0] valid_z;

4
rtl/VX_execute.v
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@@ -22,7 +22,7 @@ module VX_execute (
input wire in_jal, input wire in_jal,
input wire[31:0] in_jal_offset, input wire[31:0] in_jal_offset,
input wire[31:0] in_curr_PC, input wire[31:0] in_curr_PC,
input wire[`NT_M1:0] in_valid, input wire in_valid[`NT_M1:0],
output wire[11:0] out_csr_address, output wire[11:0] out_csr_address,
output wire out_is_csr, output wire out_is_csr,
@@ -40,7 +40,7 @@ module VX_execute (
output wire[31:0] out_branch_offset, output wire[31:0] out_branch_offset,
output wire out_branch_stall, output wire out_branch_stall,
output wire[31:0] out_PC_next, output wire[31:0] out_PC_next,
output wire[`NT_M1:0] out_valid output wire out_valid[`NT_M1:0]
); );

7
rtl/VX_f_d_reg.v
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@@ -5,13 +5,14 @@ module VX_f_d_reg (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire[31:0] in_instruction, input wire[31:0] in_instruction,
input wire[`NT_M1:0] in_valid, input wire in_valid[`NT_M1:0],
input wire[31:0] in_curr_PC, input wire[31:0] in_curr_PC,
input wire in_fwd_stall, input wire in_fwd_stall,
input wire in_freeze, input wire in_freeze,
output wire[31:0] out_instruction, output wire[31:0] out_instruction,
output wire[31:0] out_curr_PC, output wire[31:0] out_curr_PC,
output wire[`NT_M1:0] out_valid output wire out_valid[`NT_M1:0]
); );
// always @(posedge clk) begin // always @(posedge clk) begin
@@ -20,7 +21,7 @@ module VX_f_d_reg (
reg[31:0] instruction; reg[31:0] instruction;
reg[31:0] curr_PC; reg[31:0] curr_PC;
reg[`NT_M1:0] valid; reg valid[`NT_M1:0];
integer reset_cur_thread = 0; integer reset_cur_thread = 0;

2
rtl/VX_fetch.v
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@@ -19,7 +19,7 @@ module VX_fetch (
output wire[31:0] out_instruction, output wire[31:0] out_instruction,
output wire out_delay, output wire out_delay,
output wire[31:0] out_curr_PC, output wire[31:0] out_curr_PC,
output wire[`NT_M1:0] out_valid output wire out_valid[`NT_M1:0]
); );

6
rtl/VX_m_w_reg.v
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@@ -12,7 +12,7 @@ module VX_m_w_reg (
input wire[4:0] in_rs2, input wire[4:0] in_rs2,
input wire[31:0] in_PC_next, input wire[31:0] in_PC_next,
input wire in_freeze, input wire in_freeze,
input wire[`NT_M1:0] in_valid, input wire in_valid[`NT_M1:0],
output wire[31:0] out_alu_result[`NT_M1:0], output wire[31:0] out_alu_result[`NT_M1:0],
output wire[31:0] out_mem_result[`NT_M1:0], // NEW output wire[31:0] out_mem_result[`NT_M1:0], // NEW
@@ -21,7 +21,7 @@ module VX_m_w_reg (
output wire[4:0] out_rs1, output wire[4:0] out_rs1,
output wire[4:0] out_rs2, output wire[4:0] out_rs2,
output wire[31:0] out_PC_next, output wire[31:0] out_PC_next,
output wire[`NT_M1:0] out_valid output wire out_valid[`NT_M1:0]
); );
@@ -33,7 +33,7 @@ module VX_m_w_reg (
reg[4:0] rs2; reg[4:0] rs2;
reg[1:0] wb; reg[1:0] wb;
reg[31:0] PC_next; reg[31:0] PC_next;
reg[`NT_M1:0] valid; reg valid[`NT_M1:0];
initial begin initial begin

6
rtl/VX_memory.v
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@@ -15,7 +15,7 @@ module VX_memory (
input wire[31:0] in_curr_PC, input wire[31:0] in_curr_PC,
input wire[31:0] in_branch_offset, input wire[31:0] in_branch_offset,
input wire[2:0] in_branch_type, input wire[2:0] in_branch_type,
input wire[`NT_M1:0] in_valid, input wire in_valid[`NT_M1:0],
input wire[31:0] in_cache_driver_out_data[`NT_M1:0], input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
output wire[31:0] out_alu_result[`NT_M1:0], output wire[31:0] out_alu_result[`NT_M1:0],
@@ -28,11 +28,11 @@ module VX_memory (
output wire[31:0] out_branch_dest, output wire[31:0] out_branch_dest,
output wire out_delay, output wire out_delay,
output wire[31:0] out_PC_next, output wire[31:0] out_PC_next,
output wire[`NT_M1:0] out_valid, output wire out_valid[`NT_M1:0],
output wire[31:0] out_cache_driver_in_address[`NT_M1:0], output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
output wire[2:0] out_cache_driver_in_mem_read, output wire[2:0] out_cache_driver_in_mem_read,
output wire[2:0] out_cache_driver_in_mem_write, output wire[2:0] out_cache_driver_in_mem_write,
output wire[`NT_M1:0] out_cache_driver_in_valid, output wire out_cache_driver_in_valid[`NT_M1:0],
output wire[31:0] out_cache_driver_in_data[`NT_M1:0] output wire[31:0] out_cache_driver_in_data[`NT_M1:0]
); );

18
rtl/Vortex.v
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@@ -10,7 +10,7 @@ module Vortex(
output wire[31:0] out_cache_driver_in_address[`NT_M1:0], output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
output wire[2:0] out_cache_driver_in_mem_read, output wire[2:0] out_cache_driver_in_mem_read,
output wire[2:0] out_cache_driver_in_mem_write, output wire[2:0] out_cache_driver_in_mem_write,
output wire[`NT_M1:0] out_cache_driver_in_valid, output wire out_cache_driver_in_valid[`NT_M1:0],
output wire[31:0] out_cache_driver_in_data[`NT_M1:0] output wire[31:0] out_cache_driver_in_data[`NT_M1:0]
); );
@@ -21,12 +21,12 @@ assign curr_PC = fetch_curr_PC;
wire[31:0] fetch_instruction; wire[31:0] fetch_instruction;
wire fetch_delay; wire fetch_delay;
wire[31:0] fetch_curr_PC; wire[31:0] fetch_curr_PC;
wire[`NT_M1:0] fetch_valid; wire fetch_valid[`NT_M1:0];
// From f_d_register // From f_d_register
wire[31:0] f_d_instruction; wire[31:0] f_d_instruction;
wire[31:0] f_d_curr_PC; wire[31:0] f_d_curr_PC;
wire[`NT_M1:0] f_d_valid; wire f_d_valid[`NT_M1:0];
// From decode // From decode
wire decode_branch_stall; wire decode_branch_stall;
@@ -48,7 +48,7 @@ reg decode_jal;
reg[31:0] decode_jal_offset; reg[31:0] decode_jal_offset;
reg[19:0] decode_upper_immed; reg[19:0] decode_upper_immed;
wire[31:0] decode_PC_next; wire[31:0] decode_PC_next;
wire[`NT_M1:0] decode_valid; wire decode_valid[`NT_M1:0];
// From d_e_register // From d_e_register
wire[11:0] d_e_csr_address; wire[11:0] d_e_csr_address;
@@ -70,7 +70,7 @@ wire[31:0] d_e_curr_PC;
wire d_e_jal; wire d_e_jal;
wire[31:0] d_e_jal_offset; wire[31:0] d_e_jal_offset;
wire[31:0] d_e_PC_next; wire[31:0] d_e_PC_next;
wire[`NT_M1:0] d_e_valid; wire d_e_valid[`NT_M1:0];
// From execute // From execute
@@ -90,7 +90,7 @@ wire execute_jal;
wire[31:0] execute_jal_dest; wire[31:0] execute_jal_dest;
wire[31:0] execute_branch_offset; wire[31:0] execute_branch_offset;
wire[31:0] execute_PC_next; wire[31:0] execute_PC_next;
wire[`NT_M1:0] execute_valid; wire execute_valid[`NT_M1:0];
// From e_m_register // From e_m_register
@@ -113,7 +113,7 @@ wire[31:0] e_m_curr_PC;
wire[31:0] e_m_branch_offset; wire[31:0] e_m_branch_offset;
wire[2:0] e_m_branch_type; wire[2:0] e_m_branch_type;
wire[31:0] e_m_PC_next; wire[31:0] e_m_PC_next;
wire[`NT_M1:0] e_m_valid; wire e_m_valid[`NT_M1:0];
// From memory // From memory
@@ -127,7 +127,7 @@ wire[1:0] memory_wb;
wire[4:0] memory_rs1; wire[4:0] memory_rs1;
wire[4:0] memory_rs2; wire[4:0] memory_rs2;
wire[31:0] memory_PC_next; wire[31:0] memory_PC_next;
wire[`NT_M1:0] memory_valid; wire memory_valid[`NT_M1:0];
// From m_w_register // From m_w_register
wire[31:0] m_w_alu_result[`NT_M1:0]; wire[31:0] m_w_alu_result[`NT_M1:0];
@@ -139,7 +139,7 @@ wire[4:0] m_w_rs1;
wire[4:0] m_w_rs2; wire[4:0] m_w_rs2;
/* verilator lint_on UNUSED */ /* verilator lint_on UNUSED */
wire[31:0] m_w_PC_next; wire[31:0] m_w_PC_next;
wire[`NT_M1:0] m_w_valid; wire m_w_valid[`NT_M1:0];
// From writeback // From writeback
wire[31:0] writeback_write_data[`NT_M1:0]; wire[31:0] writeback_write_data[`NT_M1:0];

BIN
rtl/obj_dir/VVortex
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Binary file not shown.

606
rtl/obj_dir/VVortex.cpp
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File diff suppressed because it is too large Load Diff

42
rtl/obj_dir/VVortex.h
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@@ -25,11 +25,11 @@ VL_MODULE(VVortex) {
VL_IN8(reset,0,0); VL_IN8(reset,0,0);
VL_OUT8(out_cache_driver_in_mem_read,2,0); VL_OUT8(out_cache_driver_in_mem_read,2,0);
VL_OUT8(out_cache_driver_in_mem_write,2,0); VL_OUT8(out_cache_driver_in_mem_write,2,0);
VL_OUT8(out_cache_driver_in_valid,1,0);
VL_IN(fe_instruction,31,0); VL_IN(fe_instruction,31,0);
VL_OUT(curr_PC,31,0); VL_OUT(curr_PC,31,0);
VL_IN(in_cache_driver_out_data[2],31,0); VL_IN(in_cache_driver_out_data[2],31,0);
VL_OUT(out_cache_driver_in_address[2],31,0); VL_OUT(out_cache_driver_in_address[2],31,0);
VL_OUT8(out_cache_driver_in_valid[2],0,0);
VL_OUT(out_cache_driver_in_data[2],31,0); VL_OUT(out_cache_driver_in_data[2],31,0);
// LOCAL SIGNALS // LOCAL SIGNALS
@@ -37,7 +37,6 @@ VL_MODULE(VVortex) {
// Anonymous structures to workaround compiler member-count bugs // Anonymous structures to workaround compiler member-count bugs
struct { struct {
// Begin mtask footprint all: // Begin mtask footprint all:
VL_SIG8(Vortex__DOT__fetch_valid,1,0);
VL_SIG8(Vortex__DOT__decode_branch_type,2,0); VL_SIG8(Vortex__DOT__decode_branch_type,2,0);
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0); VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
VL_SIG8(Vortex__DOT__memory_branch_dir,0,0); VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
@@ -50,7 +49,6 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,1,0); VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,1,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid,1,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0); VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
@@ -64,8 +62,6 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__branch_type,2,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__branch_type,2,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__is_csr,0,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__jal,0,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__jal,0,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid,1,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z,1,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__stalling,0,0); VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__stalling,0,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__rd,4,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__rd,4,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__wb,1,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__wb,1,0);
@@ -74,10 +70,8 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__is_csr,0,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__branch_type,2,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__branch_type,2,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__jal,0,0); VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__jal,0,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid,1,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__rd,4,0); VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__rd,4,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__wb,1,0); VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__wb,1,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid,1,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0); VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0);
@@ -101,14 +95,14 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0); VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0); VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0); VL_SIG(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
@@ -120,30 +114,43 @@ VL_MODULE(VVortex) {
VL_SIG64(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0); VL_SIG64(Vortex__DOT__vx_execute__DOT__gen_code_label__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0); VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG8(Vortex__DOT__fetch_valid[2],0,0);
VL_SIG8(Vortex__DOT__f_d_valid[2],0,0);
VL_SIG(Vortex__DOT__decode_reg_data[4],31,0); VL_SIG(Vortex__DOT__decode_reg_data[4],31,0);
VL_SIG8(Vortex__DOT__decode_valid[2],0,0);
VL_SIG(Vortex__DOT__d_e_reg_data[4],31,0); VL_SIG(Vortex__DOT__d_e_reg_data[4],31,0);
VL_SIG8(Vortex__DOT__d_e_valid[2],0,0);
VL_SIG(Vortex__DOT__execute_alu_result[2],31,0); VL_SIG(Vortex__DOT__execute_alu_result[2],31,0);
VL_SIG(Vortex__DOT__execute_reg_data[4],31,0); VL_SIG(Vortex__DOT__execute_reg_data[4],31,0);
VL_SIG8(Vortex__DOT__execute_valid[2],0,0);
VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0); VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0);
VL_SIG(Vortex__DOT__e_m_reg_data[4],31,0); VL_SIG(Vortex__DOT__e_m_reg_data[4],31,0);
VL_SIG8(Vortex__DOT__e_m_valid[2],0,0);
VL_SIG(Vortex__DOT__memory_alu_result[2],31,0); VL_SIG(Vortex__DOT__memory_alu_result[2],31,0);
VL_SIG(Vortex__DOT__memory_mem_result[2],31,0); VL_SIG(Vortex__DOT__memory_mem_result[2],31,0);
VL_SIG8(Vortex__DOT__memory_valid[2],0,0);
VL_SIG(Vortex__DOT__m_w_alu_result[2],31,0); VL_SIG(Vortex__DOT__m_w_alu_result[2],31,0);
VL_SIG(Vortex__DOT__m_w_mem_result[2],31,0); VL_SIG(Vortex__DOT__m_w_mem_result[2],31,0);
VL_SIG8(Vortex__DOT__m_w_valid[2],0,0);
VL_SIG(Vortex__DOT__writeback_write_data[2],31,0); VL_SIG(Vortex__DOT__writeback_write_data[2],31,0);
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0); VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0); VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__use_rd2[2],31,0); VL_SIG(Vortex__DOT__use_rd2[2],31,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[2],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[2],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[32],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__0__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[32],31,0); VL_SIG(Vortex__DOT__vx_decode__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[4],31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[4],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[2],0,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[4],31,0); VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[4],31,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0); VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0); VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0); VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0); VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0);
@@ -163,28 +170,45 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data,31,0); VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0); VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0); VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[4],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[4],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[4],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[4],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[4],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[4],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[4],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0); VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0); VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0);

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34
rtl/obj_dir/VVortex__verFiles.dat
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@@ -3,24 +3,24 @@ C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_f
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 2782 12889318286 1553669148 0 1553669148 0 "VX_alu.v" S 2782 12889318286 1553669148 0 1553669148 0 "VX_alu.v"
S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v" S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v"
S 4759 12889318287 1553668670 0 1553668670 0 "VX_d_e_reg.v" S 4780 12889318287 1553672988 0 1553672988 0 "VX_d_e_reg.v"
S 10698 12889318288 1553672118 0 1553672118 0 "VX_decode.v" S 10713 12889318288 1553673019 0 1553673019 0 "VX_decode.v"
S 1551 12889079483 1553661565 0 1553661565 0 "VX_define.v" S 1551 12889079483 1553661565 0 1553661565 0 "VX_define.v"
S 3922 12889318289 1553672147 0 1553672147 0 "VX_e_m_reg.v" S 3941 12889318289 1553673060 0 1553673060 0 "VX_e_m_reg.v"
S 3350 12889318290 1553669263 0 1553669263 0 "VX_execute.v" S 3370 12889318290 1553673095 0 1553673095 0 "VX_execute.v"
S 1351 12889050060 1553664431 0 1553664431 0 "VX_f_d_reg.v" S 1382 12889050060 1553673124 0 1553673124 0 "VX_f_d_reg.v"
S 3931 12889047675 1553672617 0 1553672617 0 "VX_fetch.v" S 3941 12889047675 1553673132 0 1553673132 0 "VX_fetch.v"
S 5632 12889086478 1553672336 0 1553672336 0 "VX_forwarding.v" S 5632 12889086478 1553672336 0 1553672336 0 "VX_forwarding.v"
S 1658 12889085814 1553671325 0 1553671325 0 "VX_m_w_reg.v" S 1677 12889085814 1553673165 0 1553673165 0 "VX_m_w_reg.v"
S 2771 12889084513 1553670938 0 1553670938 0 "VX_memory.v" S 2790 12889084513 1553673201 0 1553673201 0 "VX_memory.v"
S 1000 12889070228 1553659195 0 1553659195 0 "VX_register_file.v" S 1000 12889070228 1553659195 0 1553659195 0 "VX_register_file.v"
S 1010 12889086287 1553671609 0 1553671609 0 "VX_writeback.v" S 1010 12889086287 1553671609 0 1553671609 0 "VX_writeback.v"
S 15561 12889318291 1553672234 0 1553672234 0 "Vortex.v" S 15611 12889318291 1553672889 0 1553672889 0 "Vortex.v"
T 173538 12889376662 1553672623 0 1553672623 0 "obj_dir/VVortex.cpp" T 190167 12889376837 1553673213 0 1553673213 0 "obj_dir/VVortex.cpp"
T 13367 12889376661 1553672623 0 1553672623 0 "obj_dir/VVortex.h" T 14844 12889376836 1553673213 0 1553673213 0 "obj_dir/VVortex.h"
T 1800 12889376664 1553672623 0 1553672623 0 "obj_dir/VVortex.mk" T 1800 12889376839 1553673213 0 1553673213 0 "obj_dir/VVortex.mk"
T 530 12889376660 1553672623 0 1553672623 0 "obj_dir/VVortex__Syms.cpp" T 530 12889376835 1553673213 0 1553673213 0 "obj_dir/VVortex__Syms.cpp"
T 711 12889376659 1553672623 0 1553672623 0 "obj_dir/VVortex__Syms.h" T 711 12889376834 1553673213 0 1553673213 0 "obj_dir/VVortex__Syms.h"
T 464 12889376665 1553672623 0 1553672623 0 "obj_dir/VVortex__ver.d" T 464 12889376840 1553673213 0 1553673213 0 "obj_dir/VVortex__ver.d"
T 0 0 1553672623 0 1553672623 0 "obj_dir/VVortex__verFiles.dat" T 0 0 1553673213 0 1553673213 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889376663 1553672623 0 1553672623 0 "obj_dir/VVortex_classes.mk" T 1159 12889376838 1553673213 0 1553673213 0 "obj_dir/VVortex_classes.mk"

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rtl/test_bench.h
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@@ -172,80 +172,84 @@ bool Vortex::dbus_driver()
// std::cout << "DBUS DRIVER\n" << std::endl; // std::cout << "DBUS DRIVER\n" << std::endl;
////////////////////// DBUS ////////////////////// ////////////////////// DBUS //////////////////////
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid)
{ {
for (unsigned curr_th = 0; curr_th < NT; curr_th++) if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid[curr_th])
{ {
data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th]; data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th];
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th]; addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE) if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
{ {
data_write = ( data_write) & 0xFF; data_write = ( data_write) & 0xFF;
ram.writeByte( addr, &data_write); ram.writeByte( addr, &data_write);
} else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE)
{
data_write = ( data_write) & 0xFFFF;
ram.writeHalf( addr, &data_write);
} else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE)
{
data_write = data_write;
ram.writeWord( addr, &data_write);
}
} else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE)
{
data_write = ( data_write) & 0xFFFF;
ram.writeHalf( addr, &data_write);
} else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE)
{
data_write = data_write;
ram.writeWord( addr, &data_write);
}
} }
} }
if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid)
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
{ {
for (unsigned curr_th = 0; curr_th < NT; curr_th++) if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th])
{ {
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
ram.getWord(addr, &data_read);
if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ)
{
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF); addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
ram.getWord(addr, &data_read);
} else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ) if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ)
{ {
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF); vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF);
} else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ) } else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ)
{ {
// printf("Reading mem - Addr: %h = %h\n", addr, data_read);
// std::cout << "Reading mem - Addr: " << std::hex << addr << " = " << data_read << "\n";
std::cout << std::dec;
vortex->in_cache_driver_out_data[curr_th] = data_read;
} else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ) vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF);
{
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF); } else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ)
{
// printf("Reading mem - Addr: %h = %h\n", addr, data_read);
// std::cout << "Reading mem - Addr: " << std::hex << addr << " = " << data_read << "\n";
std::cout << std::dec;
vortex->in_cache_driver_out_data[curr_th] = data_read;
} else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ) } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
{ {
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF); vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF);
} } else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ)
else {
{
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe; vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF);
}
}
else
{
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
}
} }
} else
else {
{
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe; vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
}
} }
return false; return false;
} }