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driver basic test and demo test refactoring

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This commit is contained in:
Blaise Tine
2020-06-19 09:12:07 -07:00
parent e2e1b63e14
commit 68d9fc9a75
55 changed files with 1006 additions and 1205 deletions
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160
hw/rtl/libs/VX_mult.v
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@@ -19,110 +19,102 @@ module VX_mult #(
output reg [WIDTHP-1:0] result
);
// synthesis read_comments_as_HDL on
// localparam IMPL = "quartus";
// synthesis read_comments_as_HDL off
// altera translate_off
localparam IMPL="fallback";
// altera translate_on
generate
if (IMPL == "quartus") begin
`ifdef QUARTUS
localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5;
if (FORCE_LE == "YES") begin
lpm_mult #(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult (
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
else begin
lpm_mult#(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult(
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5;
if (FORCE_LE == "YES") begin
lpm_mult #(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult (
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
else begin
lpm_mult#(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult(
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
wire [WIDTHA-1:0] dataa_pipe_end;
wire [WIDTHB-1:0] datab_pipe_end;
`else
wire [WIDTHA-1:0] dataa_pipe_end;
wire [WIDTHB-1:0] datab_pipe_end;
if (PIPELINE == 0) begin
assign dataa_pipe_end = dataa;
assign datab_pipe_end = datab;
end else begin
reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[i+1] <= 0;
datab_pipe[i+1] <= 0;
end
else if (clken) begin
dataa_pipe[i+1] <= dataa_pipe[i];
datab_pipe[i+1] <= datab_pipe[i];
end
end
end
if (PIPELINE == 0) begin
assign dataa_pipe_end = dataa;
assign datab_pipe_end = datab;
end else begin
reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[0] <= 0;
datab_pipe[0] <= 0;
dataa_pipe[i+1] <= 0;
datab_pipe[i+1] <= 0;
end
else if (clken) begin
dataa_pipe[0] <= dataa;
datab_pipe[0] <= datab;
dataa_pipe[i+1] <= dataa_pipe[i];
datab_pipe[i+1] <= datab_pipe[i];
end
end
assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
assign datab_pipe_end = datab_pipe[PIPELINE-1];
end
/* * * * * * * * * * * * * * * * * * * * * * */
/* Do the actual fallback computation here */
/* * * * * * * * * * * * * * * * * * * * * * */
if (REP == "SIGNED") begin
assign result = $signed($signed(dataa_pipe_end)*$signed(datab_pipe_end));
end
else begin
assign result = dataa_pipe_end*datab_pipe_end;
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[0] <= 0;
datab_pipe[0] <= 0;
end
else if (clken) begin
dataa_pipe[0] <= dataa;
datab_pipe[0] <= datab;
end
end
assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
assign datab_pipe_end = datab_pipe[PIPELINE-1];
end
/* * * * * * * * * * * * * * * * * * * * * * */
/* Do the actual fallback computation here */
/* * * * * * * * * * * * * * * * * * * * * * */
if (REP == "SIGNED") begin
assign result = $signed($signed(dataa_pipe_end)*$signed(datab_pipe_end));
end
else begin
assign result = dataa_pipe_end * datab_pipe_end;
end
`endif
endgenerate
endmodule: VX_mult