driver basic test and demo test refactoring
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@@ -1,9 +1,11 @@
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`include "VX_define.vh"
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module Vortex_Socket (
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`SCOPE_SIGNALS_ICACHE_IO
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`SCOPE_SIGNALS_DCACHE_IO
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`SCOPE_SIGNALS_ISTAGE_IO
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`SCOPE_SIGNALS_LSU_IO
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`SCOPE_SIGNALS_CORE_IO
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`SCOPE_SIGNALS_ICACHE_IO
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`SCOPE_SIGNALS_PIPELINE_IO
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`SCOPE_SIGNALS_BE_IO
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// Clock
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@@ -61,10 +63,12 @@ module Vortex_Socket (
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Vortex_Cluster #(
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.CLUSTER_ID(`L3CACHE_ID)
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) Vortex_Cluster (
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`SCOPE_SIGNALS_ICACHE_ATTACH
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`SCOPE_SIGNALS_DCACHE_ATTACH
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`SCOPE_SIGNALS_CORE_ATTACH
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`SCOPE_SIGNALS_BE_ATTACH
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`SCOPE_SIGNALS_ISTAGE_BIND
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`SCOPE_SIGNALS_LSU_BIND
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`SCOPE_SIGNALS_CORE_BIND
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`SCOPE_SIGNALS_ICACHE_BIND
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`SCOPE_SIGNALS_PIPELINE_BIND
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`SCOPE_SIGNALS_BE_BIND
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.clk (clk),
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.reset (reset),
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@@ -155,10 +159,12 @@ module Vortex_Socket (
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Vortex_Cluster #(
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.CLUSTER_ID(i)
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) Vortex_Cluster (
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`SCOPE_SIGNALS_ICACHE_ATTACH
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`SCOPE_SIGNALS_DCACHE_ATTACH
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`SCOPE_SIGNALS_CORE_ATTACH
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`SCOPE_SIGNALS_BE_ATTACH
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`SCOPE_SIGNALS_ISTAGE_BIND
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`SCOPE_SIGNALS_LSU_BIND
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`SCOPE_SIGNALS_CORE_BIND
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`SCOPE_SIGNALS_ICACHE_BIND
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`SCOPE_SIGNALS_PIPELINE_BIND
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`SCOPE_SIGNALS_BE_BIND
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.clk (clk),
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.reset (reset),
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@@ -387,7 +393,7 @@ module Vortex_Socket (
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end
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`ifdef DBG_PRINT_DRAM
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always_ff @(posedge clk) begin
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always @(posedge clk) begin
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if (dram_req_valid && dram_req_ready) begin
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$display("%t: DRAM req: rw=%b addr=%0h, tag=%0h, byteen=%0h data=%0h", $time, dram_req_rw, `DRAM_TO_BYTE_ADDR(dram_req_addr), dram_req_tag, dram_req_byteen, dram_req_data);
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end
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