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driver basic test and demo test refactoring

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This commit is contained in:
Blaise Tine
2020-06-19 09:12:07 -07:00
parent e2e1b63e14
commit 68d9fc9a75
55 changed files with 1006 additions and 1205 deletions
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22
hw/rtl/Vortex.v
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@@ -3,9 +3,11 @@
module Vortex #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_CORE_IO
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_PIPELINE_IO
`SCOPE_SIGNALS_BE_IO
// Clock
@@ -169,10 +171,10 @@ module Vortex #(
VX_pipeline #(
.CORE_ID(CORE_ID)
) pipeline (
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_PIPELINE_BIND
`SCOPE_SIGNALS_BE_BIND
.clk(clk),
.reset(reset),
@@ -232,9 +234,11 @@ module Vortex #(
assign snp_rsp_tag = dcache_snp_rsp_if.snp_rsp_tag;
assign dcache_snp_rsp_if.snp_rsp_ready = snp_rsp_ready;
VX_mem_ctrl #(
VX_mem_unit #(
.CORE_ID(CORE_ID)
) mem_ctrl (
) mem_unit (
`SCOPE_SIGNALS_ICACHE_BIND
.clk (clk),
.reset (reset),
@@ -269,7 +273,7 @@ module Vortex #(
.core_io_rsp_if (arb_io_rsp_if),
.core_rsp_if (core_dcache_rsp_if)
);
endmodule // Vortex