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Instruction Multiplex LSU/EXU 1 cycle DONE

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This commit is contained in:
felsabbagh3
2019-10-17 22:29:21 -04:00
parent 62db9ae691
commit 6779d0fade
18 changed files with 712 additions and 491 deletions
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49
rtl/pipe_regs/VX_e_m_reg.v
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@@ -1,49 +0,0 @@
`include "VX_define.v"
module VX_e_m_reg (
input wire clk,
input wire reset,
input wire in_freeze,
input wire[11:0] in_csr_address,
input wire in_is_csr,
input wire[31:0] in_csr_result,
input wire in_jal,
input wire[31:0] in_jal_dest,
VX_mem_req_inter VX_exe_mem_req,
VX_mem_req_inter VX_mem_req,
output wire[11:0] out_csr_address,
output wire out_is_csr,
output wire[31:0] out_csr_result,
output wire out_jal,
output wire[31:0] out_jal_dest
);
wire flush = 0;
wire stall = in_freeze;
wire temp_out_jal;
assign out_jal = temp_out_jal && VX_mem_req.valid[0];
VX_generic_register #(.N(463)) f_d_reg
(
.clk (clk),
.reset(reset),
.stall(stall),
.flush(flush),
.in ({in_csr_address , in_is_csr , in_csr_result , in_jal , in_jal_dest , VX_exe_mem_req.alu_result, VX_exe_mem_req.mem_read, VX_exe_mem_req.mem_write, VX_exe_mem_req.rd, VX_exe_mem_req.wb, VX_exe_mem_req.rs1, VX_exe_mem_req.rs2, VX_exe_mem_req.rd2, VX_exe_mem_req.PC_next, VX_exe_mem_req.curr_PC, VX_exe_mem_req.branch_offset, VX_exe_mem_req.branch_type, VX_exe_mem_req.valid, VX_exe_mem_req.warp_num}),
.out ({out_csr_address, out_is_csr, out_csr_result, temp_out_jal, out_jal_dest, VX_mem_req.alu_result , VX_mem_req.mem_read , VX_mem_req.mem_write , VX_mem_req.rd , VX_mem_req.wb , VX_mem_req.rs1 , VX_mem_req.rs2 , VX_mem_req.rd2 , VX_mem_req.PC_next , VX_mem_req.curr_PC , VX_mem_req.branch_offset , VX_mem_req.branch_type , VX_mem_req.valid , VX_mem_req.warp_num})
);
endmodule // VX_e_m_reg

33
rtl/pipe_regs/VX_m_w_reg.v
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@@ -1,33 +0,0 @@
`include "VX_define.v"
module VX_m_w_reg (
input wire clk,
input wire reset,
input wire in_freeze,
VX_inst_mem_wb_inter VX_mem_wb,
VX_mw_wb_inter VX_mw_wb
);
wire flush = 0;
wire stall = in_freeze;
VX_generic_register #(.N(303)) m_w_reg
(
.clk (clk),
.reset(reset),
.stall(stall),
.flush(flush),
.in ({VX_mem_wb.alu_result, VX_mem_wb.mem_result, VX_mem_wb.rd, VX_mem_wb.wb, VX_mem_wb.PC_next, VX_mem_wb.valid, VX_mem_wb.warp_num}),
.out ({VX_mw_wb.alu_result , VX_mw_wb.mem_result , VX_mw_wb.rd , VX_mw_wb.wb , VX_mw_wb.PC_next , VX_mw_wb.valid , VX_mw_wb.warp_num })
);
endmodule // VX_m_w_reg