diff --git a/hw/rtl/VX_decode.sv b/hw/rtl/VX_decode.sv index bd01b273..4f7b3164 100644 --- a/hw/rtl/VX_decode.sv +++ b/hw/rtl/VX_decode.sv @@ -375,6 +375,13 @@ module VX_decode #( `USED_IREG (rs1); `USED_IREG (rs2); end + 3'h5: begin + ex_type = `EX_LSU; + op_type = `INST_OP_BITS'(`INST_GPU_PRED); + imm = {{20{u_12[11]}}, u_12}; + use_rd = 0; + `USED_IREG (rs1); + end default:; endcase end diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 406f4f02..cedb7594 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -151,6 +151,7 @@ `define INST_LSU_FMT(x) x[2:0] `define INST_LSU_WSIZE(x) x[1:0] `define INST_LSU_IS_FENCE(x) x[0] +`define INST_LSU_IS_PREF(x) (x==3'b111) `define INST_FENCE_BITS 1 `define INST_FENCE_D 1'h0 diff --git a/hw/rtl/VX_instr_demux.sv b/hw/rtl/VX_instr_demux.sv index b761e9d9..3578e8d1 100644 --- a/hw/rtl/VX_instr_demux.sv +++ b/hw/rtl/VX_instr_demux.sv @@ -60,17 +60,18 @@ module VX_instr_demux ( wire lsu_req_valid = ibuffer_if.valid && (ibuffer_if.ex_type == `EX_LSU); wire [`INST_LSU_BITS-1:0] lsu_op_type = `INST_LSU_BITS'(ibuffer_if.op_type); wire lsu_is_fence = `INST_LSU_IS_FENCE(ibuffer_if.op_mod); + wire lsu_is_prefetch = (~ibuffer_if.wb) && ~(ibuffer_if.op_type[`INST_OP_BITS-1]); VX_skid_buffer #( - .DATAW (`NW_BITS + `NUM_THREADS + 32 + `INST_LSU_BITS + 1 + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)), + .DATAW (`NW_BITS + `NUM_THREADS + 32 + `INST_LSU_BITS + 1 + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32) + 1), .OUT_REG (1) ) lsu_buffer ( .clk (clk), .reset (reset), .valid_in (lsu_req_valid), .ready_in (lsu_req_ready), - .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, lsu_op_type, lsu_is_fence, ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}), - .data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.is_fence, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}), + .data_in ({ibuffer_if.wid, ibuffer_if.tmask, ibuffer_if.PC, lsu_op_type, lsu_is_fence, ibuffer_if.imm, ibuffer_if.rd, ibuffer_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data, lsu_is_prefetch}), + .data_out ({lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.is_fence, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data, lsu_req_if.is_prefetch}), .valid_out (lsu_req_if.valid), .ready_out (lsu_req_if.ready) ); diff --git a/hw/rtl/VX_lsu_unit.sv b/hw/rtl/VX_lsu_unit.sv index de05a60c..b636158b 100644 --- a/hw/rtl/VX_lsu_unit.sv +++ b/hw/rtl/VX_lsu_unit.sv @@ -40,6 +40,7 @@ module VX_lsu_unit #( wire [`NW_BITS-1:0] req_wid; wire [31:0] req_pc; wire req_is_dup; + wire req_is_prefetch; wire mbuf_empty; @@ -80,14 +81,14 @@ module VX_lsu_unit #( wire lsu_valid = lsu_req_if.valid && ~fence_wait; VX_pipe_register #( - .DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + (`NUM_THREADS * ADDR_TYPEW) + `INST_LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)), + .DATAW (1 + 1 + 1 + `NW_BITS + `NUM_THREADS + 32 + (`NUM_THREADS * 32) + (`NUM_THREADS * ADDR_TYPEW) + `INST_LSU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32)), .RESETW (1) ) req_pipe_reg ( .clk (clk), .reset (reset), .enable (!stall_in), - .data_in ({lsu_valid, lsu_is_dup, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, full_addr, lsu_addr_type, lsu_req_if.op_type, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.store_data}), - .data_out ({req_valid, req_is_dup, req_wid, req_tmask, req_pc, req_addr, req_addr_type, req_type, req_rd, req_wb, req_data}) + .data_in ({lsu_valid, lsu_is_dup, lsu_req_if.is_prefetch, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, full_addr, lsu_addr_type, lsu_req_if.op_type, lsu_req_if.rd, lsu_req_if.wb | lsu_req_if.is_prefetch, lsu_req_if.store_data}), + .data_out ({req_valid, req_is_dup, req_is_prefetch, req_wid, req_tmask, req_pc, req_addr, req_addr_type, req_type, req_rd, req_wb, req_data}) ); // Can accept new request? @@ -99,6 +100,7 @@ module VX_lsu_unit #( wire rsp_wb; wire [`INST_LSU_BITS-1:0] rsp_type; wire rsp_is_dup; + wire rsp_is_prefetch; `UNUSED_VAR (rsp_type) @@ -133,7 +135,7 @@ module VX_lsu_unit #( assign mbuf_raddr = dcache_rsp_if.tag[ADDR_TYPEW +: `LSUQ_ADDR_BITS]; VX_index_buffer #( - .DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `INST_LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1), + .DATAW (`NW_BITS + 32 + `NUM_THREADS + `NR_BITS + 1 + `INST_LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1 + 1), .SIZE (`LSUQ_SIZE) ) req_metadata ( .clk (clk), @@ -141,8 +143,8 @@ module VX_lsu_unit #( .write_addr (mbuf_waddr), .acquire_slot (mbuf_push), .read_addr (mbuf_raddr), - .write_data ({req_wid, req_pc, req_tmask, req_rd, req_wb, req_type, req_offset, req_is_dup}), - .read_data ({rsp_wid, rsp_pc, rsp_tmask, rsp_rd, rsp_wb, rsp_type, rsp_offset, rsp_is_dup}), + .write_data ({req_wid, req_pc, req_tmask, req_rd, req_wb, req_type, req_offset, req_is_dup, req_is_prefetch}), + .read_data ({rsp_wid, rsp_pc, rsp_tmask, rsp_rd, rsp_wb, rsp_type, rsp_offset, rsp_is_dup, rsp_is_prefetch}), .release_addr (mbuf_raddr), .release_slot (mbuf_pop), .full (mbuf_full), @@ -274,6 +276,8 @@ module VX_lsu_unit #( // send load commit + // ignore responce from software prefetch + wire rsp_valid = (rsp_is_prefetch)? 0:(| dcache_rsp_if.valid); wire load_rsp_stall = ~ld_commit_if.ready && ld_commit_if.valid; VX_pipe_register #( @@ -283,12 +287,12 @@ module VX_lsu_unit #( .clk (clk), .reset (reset), .enable (!load_rsp_stall), - .data_in ({dcache_rsp_if.valid, rsp_wid, rsp_tmask_qual, rsp_pc, rsp_rd, rsp_wb, rsp_data, mbuf_pop}), + .data_in ({rsp_valid, rsp_wid, rsp_tmask_qual, rsp_pc, rsp_rd, rsp_wb, rsp_data, mbuf_pop}), .data_out ({ld_commit_if.valid, ld_commit_if.wid, ld_commit_if.tmask, ld_commit_if.PC, ld_commit_if.rd, ld_commit_if.wb, ld_commit_if.data, ld_commit_if.eop}) ); // Can accept new cache response? - assign dcache_rsp_if.ready = ~load_rsp_stall; + assign dcache_rsp_if.ready = rsp_is_prefetch ? 1 : ~load_rsp_stall; // scope registration `SCOPE_ASSIGN (dcache_req_fire, dcache_req_fire); @@ -345,7 +349,7 @@ module VX_lsu_unit #( `TRACE_ARRAY1D(dcache_req_if.data, `NUM_THREADS); dpi_trace("\n"); end else begin - dpi_trace("%d: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_wid, req_pc, dcache_req_fire); + dpi_trace("%d: D$%0d Rd Req: req_is_prefetch=%b, wid=%0d, PC=%0h, tmask=%b, addr=", $time, CORE_ID, req_is_prefetch, req_wid, req_pc, dcache_req_fire); `TRACE_ARRAY1D(req_addr, `NUM_THREADS); dpi_trace(", tag=%0h, byteen=%0h, type=", req_tag, dcache_req_if.byteen); `TRACE_ARRAY1D(req_addr_type, `NUM_THREADS); @@ -353,8 +357,8 @@ module VX_lsu_unit #( end end if (dcache_rsp_fire) begin - dpi_trace("%d: D$%0d Rsp: wid=%0d, PC=%0h, tmask=%b, tag=%0h, rd=%0d, data=", - $time, CORE_ID, rsp_wid, rsp_pc, dcache_rsp_if.tmask, mbuf_raddr, rsp_rd); + dpi_trace("%d: D$%0d Rsp: rsp_is_prefetch=%b, wid=%0d, PC=%0h, tmask=%b, tag=%0h, rd=%0d, data=", + $time, CORE_ID, rsp_is_prefetch, rsp_wid, rsp_pc, dcache_rsp_if.tmask, mbuf_raddr, rsp_rd); `TRACE_ARRAY1D(dcache_rsp_if.data, `NUM_THREADS); dpi_trace(", is_dup=%b\n", rsp_is_dup); end diff --git a/hw/rtl/interfaces/VX_lsu_req_if.sv b/hw/rtl/interfaces/VX_lsu_req_if.sv index 36b4e778..4f31b17c 100644 --- a/hw/rtl/interfaces/VX_lsu_req_if.sv +++ b/hw/rtl/interfaces/VX_lsu_req_if.sv @@ -17,6 +17,7 @@ interface VX_lsu_req_if (); wire [`NR_BITS-1:0] rd; wire wb; wire ready; + wire is_prefetch; modport master ( output valid, @@ -30,6 +31,7 @@ interface VX_lsu_req_if (); output offset, output rd, output wb, + output is_prefetch, input ready ); @@ -45,6 +47,7 @@ interface VX_lsu_req_if (); input offset, input rd, input wb, + input is_prefetch, output ready ); diff --git a/runtime/include/vx_intrinsics.h b/runtime/include/vx_intrinsics.h index a1869318..5c10b6c9 100644 --- a/runtime/include/vx_intrinsics.h +++ b/runtime/include/vx_intrinsics.h @@ -84,6 +84,11 @@ inline void vx_barrier(unsigned barried_id, unsigned num_warps) { asm volatile (".insn s 0x6b, 4, %1, 0(%0)" :: "r"(barried_id), "r"(num_warps)); } +// Prefetch +inline void vx_prefetch(unsigned addr) { + asm volatile (".insn s 0x6b, 5, x0, 0(%0)" :: "r"(addr) ); +} + // Return active warp's thread id inline int vx_thread_id() { int result; diff --git a/sim/simX/decode.cpp b/sim/simX/decode.cpp index 01570aab..c23427bb 100644 --- a/sim/simX/decode.cpp +++ b/sim/simX/decode.cpp @@ -182,6 +182,7 @@ static const char* op_string(const Instr &instr) { case 2: return "SPLIT"; case 3: return "JOIN"; case 4: return "BAR"; + case 5: return "PREFETCH"; default: std::abort(); } diff --git a/sim/simX/execute.cpp b/sim/simX/execute.cpp index 01271e59..c3f9ba0f 100644 --- a/sim/simX/execute.cpp +++ b/sim/simX/execute.cpp @@ -712,6 +712,11 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { pipeline->stall_warp = true; runOnce = true; } break; + case 5: { + // PREFETCH + int addr = rsdata[0]; + printf("*** PREFETCHED %d ***\n", addr); + } break; default: std::abort(); }