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multi-ported cache support for streaming

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This commit is contained in:
Blaise Tine
2021-02-08 16:13:32 -08:00
parent fd1726197b
commit 665b97b810
13 changed files with 387 additions and 217 deletions
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22
hw/rtl/cache/VX_miss_resrv.v vendored
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@@ -1,25 +1,27 @@
`include "VX_cache_config.vh"
module VX_miss_resrv #(
parameter CACHE_ID = 0,
parameter BANK_ID = 0,
parameter CACHE_ID = 0,
parameter BANK_ID = 0,
// Number of Word requests per cycle
parameter NUM_REQS = 1,
parameter NUM_REQS = 1,
// Size of line inside a bank in bytes
parameter CACHE_LINE_SIZE = 1,
parameter CACHE_LINE_SIZE = 1,
// Number of banks
parameter NUM_BANKS = 1,
parameter NUM_BANKS = 1,
// Number of ports per banks
parameter NUM_PORTS = 1,
// Size of a word in bytes
parameter WORD_SIZE = 1,
parameter WORD_SIZE = 1,
// Miss Reserv Queue Knob
parameter MSHR_SIZE = 1,
parameter ALM_FULL = (MSHR_SIZE-1),
parameter MSHR_SIZE = 1,
parameter ALM_FULL = (MSHR_SIZE-1),
// core request tag size
parameter CORE_TAG_WIDTH = 1,
parameter CORE_TAG_WIDTH = 1,
// size of tag id in core request tag
parameter CORE_TAG_ID_BITS = 0
parameter CORE_TAG_ID_BITS = 0
) (
input wire clk,
input wire reset,