multi-ported cache support for streaming
This commit is contained in:
22
hw/rtl/cache/VX_data_access.v
vendored
22
hw/rtl/cache/VX_data_access.v
vendored
@@ -14,9 +14,7 @@ module VX_data_access #(
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Enable write-through
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parameter WRITE_THROUGH = 1,
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = 0
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parameter WRITE_THROUGH = 1
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) (
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input wire clk,
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input wire reset,
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@@ -39,8 +37,7 @@ module VX_data_access #(
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// writing
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input wire writeen,
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input wire is_fill,
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input wire [`UP(`WORD_SELECT_BITS)-1:0] wsel,
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input wire [WORD_SIZE-1:0] byteen,
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input wire [CACHE_LINE_SIZE-1:0] byteen,
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input wire [`CACHE_LINE_WIDTH-1:0] wrdata
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);
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`UNUSED_VAR (reset)
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@@ -63,19 +60,8 @@ module VX_data_access #(
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.din(wrdata),
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.dout(rddata)
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);
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wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] byteen_qual;
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if (`WORD_SELECT_BITS != 0) begin
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for (genvar i = 0; i < `WORDS_PER_LINE; i++) begin
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assign byteen_qual[i] = (wsel == `WORD_SELECT_BITS'(i)) ? byteen : {WORD_SIZE{1'b0}};
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end
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end else begin
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`UNUSED_VAR (wsel)
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assign byteen_qual = byteen;
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end
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assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen_qual;
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assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen;
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`UNUSED_VAR (readen)
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@@ -85,7 +71,7 @@ module VX_data_access #(
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if (is_fill) begin
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$display("%t: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, wrdata);
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end else begin
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$display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byte_enable, line_addr, wsel, wrdata[`WORD_WIDTH-1:0]);
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$display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), debug_wid, debug_pc, byte_enable, line_addr, wrdata);
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end
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end
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if (readen) begin
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