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minor update

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This commit is contained in:
Blaise Tine
2021-06-18 01:18:31 -07:00
parent f8dd44d180
commit 65a3704479
2 changed files with 5 additions and 2 deletions
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5
hw/rtl/VX_ibuffer.v
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@@ -109,8 +109,10 @@ module VX_ibuffer #(
// schedule the next instruction to issue // schedule the next instruction to issue
always @(*) begin always @(*) begin
deq_valid_n = 1;
if (num_warps > 1) begin if (num_warps > 1) begin
deq_valid_n = 1;
deq_wid_n = 'x;
deq_instr_n = 'x;
for (integer i = 0; i < `NUM_WARPS; i++) begin for (integer i = 0; i < `NUM_WARPS; i++) begin
if (schedule_table[i]) begin if (schedule_table[i]) begin
deq_wid_n = `NW_BITS'(i); deq_wid_n = `NW_BITS'(i);
@@ -119,6 +121,7 @@ module VX_ibuffer #(
end end
end end
end else if (1 == num_warps && !(deq_fire && q_alm_empty[deq_wid])) begin end else if (1 == num_warps && !(deq_fire && q_alm_empty[deq_wid])) begin
deq_valid_n = 1;
deq_wid_n = deq_wid; deq_wid_n = deq_wid;
deq_instr_n = deq_fire ? q_data_prev[deq_wid] : q_data_out[deq_wid]; deq_instr_n = deq_fire ? q_data_prev[deq_wid] : q_data_out[deq_wid];
end else begin end else begin

2
hw/rtl/VX_scoreboard.v
View File

@@ -14,7 +14,7 @@ module VX_scoreboard #(
reg is_reg_busy; reg is_reg_busy;
always @(*) begin always @(*) begin
is_reg_busy = 0; is_reg_busy = 'x;
for (integer i = 0; i < `NUM_WARPS; ++i) begin for (integer i = 0; i < `NUM_WARPS; ++i) begin
if (ibuf_deq_if.wid == `NW_BITS'(i)) begin if (ibuf_deq_if.wid == `NW_BITS'(i)) begin
is_reg_busy = | (inuse_regs[i] & ibuf_deq_if.used_regs); is_reg_busy = | (inuse_regs[i] & ibuf_deq_if.used_regs);