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Passing Most tests

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This commit is contained in:
felsabbagh3
2019-03-21 23:47:48 -04:00
parent d08d389177
commit 656475b3b3
49 changed files with 4425 additions and 2075 deletions
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975
rtl/obj_dir/VVX_decode.cpp
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@@ -1,975 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVX_decode.h for the primary calling header
#include "VVX_decode.h"
#include "VVX_decode__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVX_decode) {
VVX_decode__Syms* __restrict vlSymsp = __VlSymsp = new VVX_decode__Syms(this, name());
VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVX_decode::__Vconfigure(VVX_decode__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVX_decode::~VVX_decode() {
delete __VlSymsp; __VlSymsp=NULL;
}
//--------------------
void VVX_decode::eval() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_decode::eval\n"); );
VVX_decode__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
#ifdef VL_DEBUG
// Debug assertions
_eval_debug_assertions();
#endif // VL_DEBUG
// Initialize
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
void VVX_decode::_eval_initial_loop(VVX_decode__Syms* __restrict vlSymsp) {
vlSymsp->__Vm_didInit = true;
_eval_initial(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
_eval_settle(vlSymsp);
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
//--------------------
// Internal Methods
VL_INLINE_OPT void VVX_decode::_combo__TOP__1(VVX_decode__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_combo__TOP__1\n"); );
VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->out_PC_next = ((IData)(4U) + vlTOPp->in_curr_PC);
vlTOPp->out_mem_read = (7U & ((3U == (0x7fU & vlTOPp->in_instruction))
? (vlTOPp->in_instruction
>> 0xcU) : 7U));
vlTOPp->out_mem_write = (7U & ((0x23U == (0x7fU
& vlTOPp->in_instruction))
? (vlTOPp->in_instruction
>> 0xcU) : 7U));
// ALWAYS at VX_decode.v:247
vlTOPp->out_jal = ((0x6fU == (0x7fU & vlTOPp->in_instruction))
| ((0x67U == (0x7fU & vlTOPp->in_instruction))
| ((0x73U == (0x7fU & vlTOPp->in_instruction))
& ((0U == (7U & (vlTOPp->in_instruction
>> 0xcU)))
& (2U > (0xfffU & (vlTOPp->in_instruction
>> 0x14U)))))));
vlTOPp->out_csr_address = (0xfffU & (((0U != (7U
& (vlTOPp->in_instruction
>> 0xcU)))
& (2U <=
(0xfffU
& (vlTOPp->in_instruction
>> 0x14U))))
? (vlTOPp->in_instruction
>> 0x14U)
: 0x55U));
// ALWAYS at VX_decode.v:306
vlTOPp->out_branch_stall = ((0x63U == (0x7fU & vlTOPp->in_instruction))
| ((0x6fU == (0x7fU
& vlTOPp->in_instruction))
| (0x67U == (0x7fU
& vlTOPp->in_instruction))));
vlTOPp->out_rd = (0x1fU & (vlTOPp->in_instruction
>> 7U));
// ALWAYS at VX_decode.v:306
vlTOPp->out_branch_type = ((0x63U == (0x7fU & vlTOPp->in_instruction))
? ((0x4000U & vlTOPp->in_instruction)
? ((0x2000U & vlTOPp->in_instruction)
? ((0x1000U
& vlTOPp->in_instruction)
? 6U : 5U)
: ((0x1000U
& vlTOPp->in_instruction)
? 4U : 3U))
: ((0x2000U & vlTOPp->in_instruction)
? 0U : ((0x1000U
& vlTOPp->in_instruction)
? 2U
: 1U)))
: 0U);
vlTOPp->VX_decode__DOT__is_itype = ((0x13U == (0x7fU
& vlTOPp->in_instruction))
| (3U == (0x7fU
& vlTOPp->in_instruction)));
vlTOPp->VX_decode__DOT__is_csr = ((0x73U == (0x7fU
& vlTOPp->in_instruction))
& (0U != (7U
& (vlTOPp->in_instruction
>> 0xcU))));
vlTOPp->out_rs1 = (0x1fU & (vlTOPp->in_instruction
>> 0xfU));
vlTOPp->out_rs2 = (0x1fU & (vlTOPp->in_instruction
>> 0x14U));
vlTOPp->out_rs2_src = (1U & (((IData)(vlTOPp->VX_decode__DOT__is_itype)
| (0x23U == (0x7fU
& vlTOPp->in_instruction)))
? 1U : 0U));
vlTOPp->out_is_csr = vlTOPp->VX_decode__DOT__is_csr;
vlTOPp->out_wb = ((((0x6fU == (0x7fU & vlTOPp->in_instruction))
| (0x67U == (0x7fU & vlTOPp->in_instruction)))
| ((0x73U == (0x7fU & vlTOPp->in_instruction))
& (0U == (7U & (vlTOPp->in_instruction
>> 0xcU)))))
? 3U : ((3U == (0x7fU & vlTOPp->in_instruction))
? 2U : ((((((IData)(vlTOPp->VX_decode__DOT__is_itype)
| (0x33U
== (0x7fU
& vlTOPp->in_instruction)))
| (0x37U
== (0x7fU
& vlTOPp->in_instruction)))
| (0x17U
== (0x7fU
& vlTOPp->in_instruction)))
| (IData)(vlTOPp->VX_decode__DOT__is_csr))
? 1U : 0U)));
vlTOPp->out_alu_op = ((0x63U == (0x7fU & vlTOPp->in_instruction))
? ((5U > (IData)(vlTOPp->out_branch_type))
? 1U : 0xaU) : ((0x37U
==
(0x7fU
& vlTOPp->in_instruction))
? 0xbU
: (
(0x17U
==
(0x7fU
& vlTOPp->in_instruction))
? 0xcU
:
((IData)(vlTOPp->VX_decode__DOT__is_csr)
?
((1U
==
(3U
& (vlTOPp->in_instruction
>> 0xcU)))
? 0xdU
:
((2U
==
(3U
& (vlTOPp->in_instruction
>> 0xcU)))
? 0xeU
: 0xfU))
:
(((0x23U
==
(0x7fU
& vlTOPp->in_instruction))
| (3U
==
(0x7fU
& vlTOPp->in_instruction)))
? 0U
:
((0x4000U
& vlTOPp->in_instruction)
?
((0x2000U
& vlTOPp->in_instruction)
?
((0x1000U
& vlTOPp->in_instruction)
? 9U
: 8U)
:
((0x1000U
& vlTOPp->in_instruction)
?
((0U
==
(0x7fU
& (vlTOPp->in_instruction
>> 0x19U)))
? 6U
: 7U)
: 5U))
:
((0x2000U
& vlTOPp->in_instruction)
?
((0x1000U
& vlTOPp->in_instruction)
? 4U
: 3U)
:
((0x1000U
& vlTOPp->in_instruction)
? 2U
:
((0x13U
==
(0x7fU
& vlTOPp->in_instruction))
? 0U
:
((0U
==
(0x7fU
& (vlTOPp->in_instruction
>> 0x19U)))
? 0U
: 1U))))))))));
// ALWAYS at VX_decode.v:201
vlTOPp->out_upper_immed = ((0x37U == (0x7fU & vlTOPp->in_instruction))
? ((0xfe000U & (vlTOPp->in_instruction
>> 0xcU))
| (((IData)(vlTOPp->out_rs2)
<< 8U) | (((IData)(vlTOPp->out_rs1)
<< 3U)
| (7U
& (vlTOPp->in_instruction
>> 0xcU)))))
: ((0x17U == (0x7fU
& vlTOPp->in_instruction))
? ((0xfe000U &
(vlTOPp->in_instruction
>> 0xcU))
| (((IData)(vlTOPp->out_rs2)
<< 8U) |
(((IData)(vlTOPp->out_rs1)
<< 3U)
| (7U &
(vlTOPp->in_instruction
>> 0xcU)))))
: 0U));
vlTOPp->VX_decode__DOT__jalr_immed = ((0xfe0U &
(vlTOPp->in_instruction
>> 0x14U))
| (IData)(vlTOPp->out_rs2));
vlTOPp->VX_decode__DOT__alu_tempp = (0xfffU & (
((1U
==
(7U
& (vlTOPp->in_instruction
>> 0xcU)))
| (5U
==
(7U
& (vlTOPp->in_instruction
>> 0xcU))))
? (IData)(vlTOPp->out_rs2)
:
(vlTOPp->in_instruction
>> 0x14U)));
// ALWAYS at VX_decode.v:247
vlTOPp->out_jal_offset = ((0x6fU == (0x7fU & vlTOPp->in_instruction))
? ((0xffe00000U & (VL_NEGATE_I((IData)(
(1U
& (vlTOPp->in_instruction
>> 0x1fU))))
<< 0x15U))
| ((0x100000U & (vlTOPp->in_instruction
>> 0xbU))
| ((0xff000U & vlTOPp->in_instruction)
| ((0x800U
& (vlTOPp->in_instruction
>> 9U))
| (0x7feU
& (vlTOPp->in_instruction
>> 0x14U))))))
: ((0x67U == (0x7fU
& vlTOPp->in_instruction))
? ((0xfffff000U
& (VL_NEGATE_I((IData)(
(1U
& ((IData)(vlTOPp->VX_decode__DOT__jalr_immed)
>> 0xbU))))
<< 0xcU))
| (IData)(vlTOPp->VX_decode__DOT__jalr_immed))
: ((0x73U == (0x7fU
& vlTOPp->in_instruction))
? (((0U == (7U
& (vlTOPp->in_instruction
>> 0xcU)))
& (2U >
(0xfffU
& (vlTOPp->in_instruction
>> 0x14U))))
? 0xb0000000U
: 0xdeadbeefU)
: 0xdeadbeefU)));
// ALWAYS at VX_decode.v:295
vlTOPp->out_itype_immed = ((0x40U & vlTOPp->in_instruction)
? ((0x20U & vlTOPp->in_instruction)
? ((0x10U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((8U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((4U
& vlTOPp->in_instruction)
? 0xdeadbeefU
: (
(2U
& vlTOPp->in_instruction)
?
((1U
& vlTOPp->in_instruction)
?
((0xfffff000U
& (VL_NEGATE_I((IData)(
(1U
& (vlTOPp->in_instruction
>> 0x1fU))))
<< 0xcU))
| ((0x800U
& (vlTOPp->in_instruction
>> 0x14U))
| ((0x400U
& (vlTOPp->in_instruction
<< 3U))
| ((0x3f0U
& (vlTOPp->in_instruction
>> 0x15U))
| (0xfU
& (vlTOPp->in_instruction
>> 8U))))))
: 0xdeadbeefU)
: 0xdeadbeefU))))
: 0xdeadbeefU) :
((0x20U & vlTOPp->in_instruction)
? ((0x10U & vlTOPp->in_instruction)
? 0xdeadbeefU :
((8U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((4U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((2U & vlTOPp->in_instruction)
? ((1U
& vlTOPp->in_instruction)
?
((0xfffff000U
& (VL_NEGATE_I((IData)(
(1U
& (vlTOPp->in_instruction
>> 0x1fU))))
<< 0xcU))
| ((0xfe0U
& (vlTOPp->in_instruction
>> 0x14U))
| (IData)(vlTOPp->out_rd)))
: 0xdeadbeefU)
: 0xdeadbeefU))))
: ((0x10U & vlTOPp->in_instruction)
? ((8U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((4U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((2U
& vlTOPp->in_instruction)
?
((1U
& vlTOPp->in_instruction)
?
((0xfffff000U
& (VL_NEGATE_I((IData)(
(1U
& ((IData)(vlTOPp->VX_decode__DOT__alu_tempp)
>> 0xbU))))
<< 0xcU))
| (IData)(vlTOPp->VX_decode__DOT__alu_tempp))
: 0xdeadbeefU)
: 0xdeadbeefU)))
: ((8U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((4U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((2U
& vlTOPp->in_instruction)
?
((1U
& vlTOPp->in_instruction)
?
((0xfffff000U
& (VL_NEGATE_I((IData)(
(1U
& (vlTOPp->in_instruction
>> 0x1fU))))
<< 0xcU))
| (0xfffU
& (vlTOPp->in_instruction
>> 0x14U)))
: 0xdeadbeefU)
: 0xdeadbeefU))))));
}
void VVX_decode::_settle__TOP__2(VVX_decode__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_settle__TOP__2\n"); );
VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->out_PC_next = ((IData)(4U) + vlTOPp->in_curr_PC);
vlTOPp->out_mem_read = (7U & ((3U == (0x7fU & vlTOPp->in_instruction))
? (vlTOPp->in_instruction
>> 0xcU) : 7U));
vlTOPp->out_mem_write = (7U & ((0x23U == (0x7fU
& vlTOPp->in_instruction))
? (vlTOPp->in_instruction
>> 0xcU) : 7U));
// ALWAYS at VX_decode.v:247
vlTOPp->out_jal = ((0x6fU == (0x7fU & vlTOPp->in_instruction))
| ((0x67U == (0x7fU & vlTOPp->in_instruction))
| ((0x73U == (0x7fU & vlTOPp->in_instruction))
& ((0U == (7U & (vlTOPp->in_instruction
>> 0xcU)))
& (2U > (0xfffU & (vlTOPp->in_instruction
>> 0x14U)))))));
vlTOPp->out_csr_address = (0xfffU & (((0U != (7U
& (vlTOPp->in_instruction
>> 0xcU)))
& (2U <=
(0xfffU
& (vlTOPp->in_instruction
>> 0x14U))))
? (vlTOPp->in_instruction
>> 0x14U)
: 0x55U));
// ALWAYS at VX_decode.v:306
vlTOPp->out_branch_stall = ((0x63U == (0x7fU & vlTOPp->in_instruction))
| ((0x6fU == (0x7fU
& vlTOPp->in_instruction))
| (0x67U == (0x7fU
& vlTOPp->in_instruction))));
vlTOPp->out_rd = (0x1fU & (vlTOPp->in_instruction
>> 7U));
// ALWAYS at VX_decode.v:306
vlTOPp->out_branch_type = ((0x63U == (0x7fU & vlTOPp->in_instruction))
? ((0x4000U & vlTOPp->in_instruction)
? ((0x2000U & vlTOPp->in_instruction)
? ((0x1000U
& vlTOPp->in_instruction)
? 6U : 5U)
: ((0x1000U
& vlTOPp->in_instruction)
? 4U : 3U))
: ((0x2000U & vlTOPp->in_instruction)
? 0U : ((0x1000U
& vlTOPp->in_instruction)
? 2U
: 1U)))
: 0U);
vlTOPp->VX_decode__DOT__is_itype = ((0x13U == (0x7fU
& vlTOPp->in_instruction))
| (3U == (0x7fU
& vlTOPp->in_instruction)));
vlTOPp->VX_decode__DOT__is_csr = ((0x73U == (0x7fU
& vlTOPp->in_instruction))
& (0U != (7U
& (vlTOPp->in_instruction
>> 0xcU))));
vlTOPp->out_rs1 = (0x1fU & (vlTOPp->in_instruction
>> 0xfU));
vlTOPp->out_rs2 = (0x1fU & (vlTOPp->in_instruction
>> 0x14U));
vlTOPp->out_rs2_src = (1U & (((IData)(vlTOPp->VX_decode__DOT__is_itype)
| (0x23U == (0x7fU
& vlTOPp->in_instruction)))
? 1U : 0U));
vlTOPp->out_is_csr = vlTOPp->VX_decode__DOT__is_csr;
vlTOPp->out_wb = ((((0x6fU == (0x7fU & vlTOPp->in_instruction))
| (0x67U == (0x7fU & vlTOPp->in_instruction)))
| ((0x73U == (0x7fU & vlTOPp->in_instruction))
& (0U == (7U & (vlTOPp->in_instruction
>> 0xcU)))))
? 3U : ((3U == (0x7fU & vlTOPp->in_instruction))
? 2U : ((((((IData)(vlTOPp->VX_decode__DOT__is_itype)
| (0x33U
== (0x7fU
& vlTOPp->in_instruction)))
| (0x37U
== (0x7fU
& vlTOPp->in_instruction)))
| (0x17U
== (0x7fU
& vlTOPp->in_instruction)))
| (IData)(vlTOPp->VX_decode__DOT__is_csr))
? 1U : 0U)));
vlTOPp->out_alu_op = ((0x63U == (0x7fU & vlTOPp->in_instruction))
? ((5U > (IData)(vlTOPp->out_branch_type))
? 1U : 0xaU) : ((0x37U
==
(0x7fU
& vlTOPp->in_instruction))
? 0xbU
: (
(0x17U
==
(0x7fU
& vlTOPp->in_instruction))
? 0xcU
:
((IData)(vlTOPp->VX_decode__DOT__is_csr)
?
((1U
==
(3U
& (vlTOPp->in_instruction
>> 0xcU)))
? 0xdU
:
((2U
==
(3U
& (vlTOPp->in_instruction
>> 0xcU)))
? 0xeU
: 0xfU))
:
(((0x23U
==
(0x7fU
& vlTOPp->in_instruction))
| (3U
==
(0x7fU
& vlTOPp->in_instruction)))
? 0U
:
((0x4000U
& vlTOPp->in_instruction)
?
((0x2000U
& vlTOPp->in_instruction)
?
((0x1000U
& vlTOPp->in_instruction)
? 9U
: 8U)
:
((0x1000U
& vlTOPp->in_instruction)
?
((0U
==
(0x7fU
& (vlTOPp->in_instruction
>> 0x19U)))
? 6U
: 7U)
: 5U))
:
((0x2000U
& vlTOPp->in_instruction)
?
((0x1000U
& vlTOPp->in_instruction)
? 4U
: 3U)
:
((0x1000U
& vlTOPp->in_instruction)
? 2U
:
((0x13U
==
(0x7fU
& vlTOPp->in_instruction))
? 0U
:
((0U
==
(0x7fU
& (vlTOPp->in_instruction
>> 0x19U)))
? 0U
: 1U))))))))));
vlTOPp->out_rd1 = ((0x6fU == (0x7fU & vlTOPp->in_instruction))
? vlTOPp->in_curr_PC : ((IData)(vlTOPp->in_src1_fwd)
? vlTOPp->in_src1_fwd_data
:
vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers
[vlTOPp->out_rs1]));
// ALWAYS at VX_decode.v:201
vlTOPp->out_upper_immed = ((0x37U == (0x7fU & vlTOPp->in_instruction))
? ((0xfe000U & (vlTOPp->in_instruction
>> 0xcU))
| (((IData)(vlTOPp->out_rs2)
<< 8U) | (((IData)(vlTOPp->out_rs1)
<< 3U)
| (7U
& (vlTOPp->in_instruction
>> 0xcU)))))
: ((0x17U == (0x7fU
& vlTOPp->in_instruction))
? ((0xfe000U &
(vlTOPp->in_instruction
>> 0xcU))
| (((IData)(vlTOPp->out_rs2)
<< 8U) |
(((IData)(vlTOPp->out_rs1)
<< 3U)
| (7U &
(vlTOPp->in_instruction
>> 0xcU)))))
: 0U));
vlTOPp->VX_decode__DOT__jalr_immed = ((0xfe0U &
(vlTOPp->in_instruction
>> 0x14U))
| (IData)(vlTOPp->out_rs2));
vlTOPp->VX_decode__DOT__alu_tempp = (0xfffU & (
((1U
==
(7U
& (vlTOPp->in_instruction
>> 0xcU)))
| (5U
==
(7U
& (vlTOPp->in_instruction
>> 0xcU))))
? (IData)(vlTOPp->out_rs2)
:
(vlTOPp->in_instruction
>> 0x14U)));
vlTOPp->out_rd2 = ((IData)(vlTOPp->in_src2_fwd)
? vlTOPp->in_src2_fwd_data :
vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers
[vlTOPp->out_rs2]);
vlTOPp->out_csr_mask = (((IData)(vlTOPp->VX_decode__DOT__is_csr)
& (vlTOPp->in_instruction
>> 0xeU)) ? (IData)(vlTOPp->out_rs1)
: vlTOPp->out_rd1);
// ALWAYS at VX_decode.v:247
vlTOPp->out_jal_offset = ((0x6fU == (0x7fU & vlTOPp->in_instruction))
? ((0xffe00000U & (VL_NEGATE_I((IData)(
(1U
& (vlTOPp->in_instruction
>> 0x1fU))))
<< 0x15U))
| ((0x100000U & (vlTOPp->in_instruction
>> 0xbU))
| ((0xff000U & vlTOPp->in_instruction)
| ((0x800U
& (vlTOPp->in_instruction
>> 9U))
| (0x7feU
& (vlTOPp->in_instruction
>> 0x14U))))))
: ((0x67U == (0x7fU
& vlTOPp->in_instruction))
? ((0xfffff000U
& (VL_NEGATE_I((IData)(
(1U
& ((IData)(vlTOPp->VX_decode__DOT__jalr_immed)
>> 0xbU))))
<< 0xcU))
| (IData)(vlTOPp->VX_decode__DOT__jalr_immed))
: ((0x73U == (0x7fU
& vlTOPp->in_instruction))
? (((0U == (7U
& (vlTOPp->in_instruction
>> 0xcU)))
& (2U >
(0xfffU
& (vlTOPp->in_instruction
>> 0x14U))))
? 0xb0000000U
: 0xdeadbeefU)
: 0xdeadbeefU)));
// ALWAYS at VX_decode.v:295
vlTOPp->out_itype_immed = ((0x40U & vlTOPp->in_instruction)
? ((0x20U & vlTOPp->in_instruction)
? ((0x10U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((8U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((4U
& vlTOPp->in_instruction)
? 0xdeadbeefU
: (
(2U
& vlTOPp->in_instruction)
?
((1U
& vlTOPp->in_instruction)
?
((0xfffff000U
& (VL_NEGATE_I((IData)(
(1U
& (vlTOPp->in_instruction
>> 0x1fU))))
<< 0xcU))
| ((0x800U
& (vlTOPp->in_instruction
>> 0x14U))
| ((0x400U
& (vlTOPp->in_instruction
<< 3U))
| ((0x3f0U
& (vlTOPp->in_instruction
>> 0x15U))
| (0xfU
& (vlTOPp->in_instruction
>> 8U))))))
: 0xdeadbeefU)
: 0xdeadbeefU))))
: 0xdeadbeefU) :
((0x20U & vlTOPp->in_instruction)
? ((0x10U & vlTOPp->in_instruction)
? 0xdeadbeefU :
((8U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((4U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((2U & vlTOPp->in_instruction)
? ((1U
& vlTOPp->in_instruction)
?
((0xfffff000U
& (VL_NEGATE_I((IData)(
(1U
& (vlTOPp->in_instruction
>> 0x1fU))))
<< 0xcU))
| ((0xfe0U
& (vlTOPp->in_instruction
>> 0x14U))
| (IData)(vlTOPp->out_rd)))
: 0xdeadbeefU)
: 0xdeadbeefU))))
: ((0x10U & vlTOPp->in_instruction)
? ((8U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((4U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((2U
& vlTOPp->in_instruction)
?
((1U
& vlTOPp->in_instruction)
?
((0xfffff000U
& (VL_NEGATE_I((IData)(
(1U
& ((IData)(vlTOPp->VX_decode__DOT__alu_tempp)
>> 0xbU))))
<< 0xcU))
| (IData)(vlTOPp->VX_decode__DOT__alu_tempp))
: 0xdeadbeefU)
: 0xdeadbeefU)))
: ((8U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((4U & vlTOPp->in_instruction)
? 0xdeadbeefU
: ((2U
& vlTOPp->in_instruction)
?
((1U
& vlTOPp->in_instruction)
?
((0xfffff000U
& (VL_NEGATE_I((IData)(
(1U
& (vlTOPp->in_instruction
>> 0x1fU))))
<< 0xcU))
| (0xfffU
& (vlTOPp->in_instruction
>> 0x14U)))
: 0xdeadbeefU)
: 0xdeadbeefU))))));
}
VL_INLINE_OPT void VVX_decode::_sequent__TOP__3(VVX_decode__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_sequent__TOP__3\n"); );
VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Variables
// Begin mtask footprint all:
VL_SIG8(__Vdlyvdim0__VX_decode__DOT__vx_register_file__DOT__registers__v0,4,0);
VL_SIG8(__Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0,0,0);
VL_SIG(__Vdlyvval__VX_decode__DOT__vx_register_file__DOT__registers__v0,31,0);
// Body
__Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0 = 0U;
// ALWAYS at VX_register_file.v:30
if (((0U != (IData)(vlTOPp->in_wb)) & (0U != (IData)(vlTOPp->in_rd)))) {
__Vdlyvval__VX_decode__DOT__vx_register_file__DOT__registers__v0
= vlTOPp->in_write_data;
__Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0 = 1U;
__Vdlyvdim0__VX_decode__DOT__vx_register_file__DOT__registers__v0
= vlTOPp->in_rd;
}
// ALWAYSPOST at VX_register_file.v:32
if (__Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0) {
vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers[__Vdlyvdim0__VX_decode__DOT__vx_register_file__DOT__registers__v0]
= __Vdlyvval__VX_decode__DOT__vx_register_file__DOT__registers__v0;
}
}
VL_INLINE_OPT void VVX_decode::_combo__TOP__4(VVX_decode__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_combo__TOP__4\n"); );
VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->out_rd2 = ((IData)(vlTOPp->in_src2_fwd)
? vlTOPp->in_src2_fwd_data :
vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers
[vlTOPp->out_rs2]);
vlTOPp->out_rd1 = ((0x6fU == (0x7fU & vlTOPp->in_instruction))
? vlTOPp->in_curr_PC : ((IData)(vlTOPp->in_src1_fwd)
? vlTOPp->in_src1_fwd_data
:
vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers
[vlTOPp->out_rs1]));
vlTOPp->out_csr_mask = (((IData)(vlTOPp->VX_decode__DOT__is_csr)
& (vlTOPp->in_instruction
>> 0xeU)) ? (IData)(vlTOPp->out_rs1)
: vlTOPp->out_rd1);
}
void VVX_decode::_eval(VVX_decode__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_eval\n"); );
VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->_combo__TOP__1(vlSymsp);
if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
vlTOPp->_sequent__TOP__3(vlSymsp);
}
vlTOPp->_combo__TOP__4(vlSymsp);
// Final
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}
void VVX_decode::_eval_initial(VVX_decode__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_eval_initial\n"); );
VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}
void VVX_decode::final() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::final\n"); );
// Variables
VVX_decode__Syms* __restrict vlSymsp = this->__VlSymsp;
VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void VVX_decode::_eval_settle(VVX_decode__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_eval_settle\n"); );
VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->_settle__TOP__2(vlSymsp);
}
VL_INLINE_OPT QData VVX_decode::_change_request(VVX_decode__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_change_request\n"); );
VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// Change detection
QData __req = false; // Logically a bool
return __req;
}
#ifdef VL_DEBUG
void VVX_decode::_eval_debug_assertions() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_eval_debug_assertions\n"); );
// Body
if (VL_UNLIKELY((clk & 0xfeU))) {
Verilated::overWidthError("clk");}
if (VL_UNLIKELY((in_rd & 0xe0U))) {
Verilated::overWidthError("in_rd");}
if (VL_UNLIKELY((in_wb & 0xfcU))) {
Verilated::overWidthError("in_wb");}
if (VL_UNLIKELY((in_src1_fwd & 0xfeU))) {
Verilated::overWidthError("in_src1_fwd");}
if (VL_UNLIKELY((in_src2_fwd & 0xfeU))) {
Verilated::overWidthError("in_src2_fwd");}
}
#endif // VL_DEBUG
void VVX_decode::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_decode::_ctor_var_reset\n"); );
// Body
clk = VL_RAND_RESET_I(1);
in_instruction = VL_RAND_RESET_I(32);
in_curr_PC = VL_RAND_RESET_I(32);
in_write_data = VL_RAND_RESET_I(32);
in_rd = VL_RAND_RESET_I(5);
in_wb = VL_RAND_RESET_I(2);
in_src1_fwd = VL_RAND_RESET_I(1);
in_src1_fwd_data = VL_RAND_RESET_I(32);
in_src2_fwd = VL_RAND_RESET_I(1);
in_src2_fwd_data = VL_RAND_RESET_I(32);
out_csr_address = VL_RAND_RESET_I(12);
out_is_csr = VL_RAND_RESET_I(1);
out_csr_mask = VL_RAND_RESET_I(32);
out_rd = VL_RAND_RESET_I(5);
out_rs1 = VL_RAND_RESET_I(5);
out_rd1 = VL_RAND_RESET_I(32);
out_rs2 = VL_RAND_RESET_I(5);
out_rd2 = VL_RAND_RESET_I(32);
out_wb = VL_RAND_RESET_I(2);
out_alu_op = VL_RAND_RESET_I(4);
out_rs2_src = VL_RAND_RESET_I(1);
out_itype_immed = VL_RAND_RESET_I(32);
out_mem_read = VL_RAND_RESET_I(3);
out_mem_write = VL_RAND_RESET_I(3);
out_branch_type = VL_RAND_RESET_I(3);
out_branch_stall = VL_RAND_RESET_I(1);
out_jal = VL_RAND_RESET_I(1);
out_jal_offset = VL_RAND_RESET_I(32);
out_upper_immed = VL_RAND_RESET_I(20);
out_PC_next = VL_RAND_RESET_I(32);
VX_decode__DOT__is_itype = VL_RAND_RESET_I(1);
VX_decode__DOT__is_csr = VL_RAND_RESET_I(1);
VX_decode__DOT__jalr_immed = VL_RAND_RESET_I(12);
VX_decode__DOT__alu_tempp = VL_RAND_RESET_I(12);
{ int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
VX_decode__DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
}}
}

118
rtl/obj_dir/VVX_decode.h
View File

@@ -1,118 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _VVX_decode_H_
#define _VVX_decode_H_
#include "verilated.h"
class VVX_decode__Syms;
//----------
VL_MODULE(VVX_decode) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
// Begin mtask footprint all:
VL_IN8(clk,0,0);
VL_IN8(in_rd,4,0);
VL_IN8(in_wb,1,0);
VL_IN8(in_src1_fwd,0,0);
VL_IN8(in_src2_fwd,0,0);
VL_OUT8(out_is_csr,0,0);
VL_OUT8(out_rd,4,0);
VL_OUT8(out_rs1,4,0);
VL_OUT8(out_rs2,4,0);
VL_OUT8(out_wb,1,0);
VL_OUT8(out_alu_op,3,0);
VL_OUT8(out_rs2_src,0,0);
VL_OUT8(out_mem_read,2,0);
VL_OUT8(out_mem_write,2,0);
VL_OUT8(out_branch_type,2,0);
VL_OUT8(out_branch_stall,0,0);
VL_OUT8(out_jal,0,0);
VL_OUT16(out_csr_address,11,0);
VL_IN(in_instruction,31,0);
VL_IN(in_curr_PC,31,0);
VL_IN(in_write_data,31,0);
VL_IN(in_src1_fwd_data,31,0);
VL_IN(in_src2_fwd_data,31,0);
VL_OUT(out_csr_mask,31,0);
VL_OUT(out_rd1,31,0);
VL_OUT(out_rd2,31,0);
VL_OUT(out_itype_immed,31,0);
VL_OUT(out_jal_offset,31,0);
VL_OUT(out_upper_immed,19,0);
VL_OUT(out_PC_next,31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(VX_decode__DOT__is_itype,0,0);
VL_SIG8(VX_decode__DOT__is_csr,0,0);
VL_SIG16(VX_decode__DOT__jalr_immed,11,0);
VL_SIG16(VX_decode__DOT__alu_tempp,11,0);
VL_SIG(VX_decode__DOT__vx_register_file__DOT__registers[32],31,0);
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(__Vclklast__TOP__clk,0,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
VVX_decode__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVX_decode); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
VVX_decode(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~VVX_decode();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(VVX_decode__Syms* __restrict vlSymsp);
public:
void __Vconfigure(VVX_decode__Syms* symsp, bool first);
private:
static QData _change_request(VVX_decode__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__1(VVX_decode__Syms* __restrict vlSymsp);
static void _combo__TOP__4(VVX_decode__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset();
public:
static void _eval(VVX_decode__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(VVX_decode__Syms* __restrict vlSymsp);
static void _eval_settle(VVX_decode__Syms* __restrict vlSymsp);
static void _sequent__TOP__3(VVX_decode__Syms* __restrict vlSymsp);
static void _settle__TOP__2(VVX_decode__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(128);
#endif // guard

53
rtl/obj_dir/VVX_decode.mk
View File

@@ -1,53 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f VVX_decode.mk
default: VVX_decode__ALL.a
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = VVX_decode
# Module prefix (from --prefix)
VM_MODPREFIX = VVX_decode
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
### Default rules...
# Include list of all generated classes
include VVX_decode_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
# Verilated -*- Makefile -*-

19
rtl/obj_dir/VVX_decode__Syms.cpp
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@@ -1,19 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "VVX_decode__Syms.h"
#include "VVX_decode.h"
// FUNCTIONS
VVX_decode__Syms::VVX_decode__Syms(VVX_decode* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
}

34
rtl/obj_dir/VVX_decode__Syms.h
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@@ -1,34 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header
#ifndef _VVX_decode__Syms_H_
#define _VVX_decode__Syms_H_
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "VVX_decode.h"
// SYMS CLASS
class VVX_decode__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_didInit;
// SUBCELL STATE
VVX_decode* TOPp;
// CREATORS
VVX_decode__Syms(VVX_decode* topp, const char* namep);
~VVX_decode__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
} VL_ATTR_ALIGNED(64);
#endif // guard

1
rtl/obj_dir/VVX_decode__ver.d
View File

@@ -1 +0,0 @@
obj_dir/VVX_decode.cpp obj_dir/VVX_decode.h obj_dir/VVX_decode.mk obj_dir/VVX_decode__Syms.cpp obj_dir/VVX_decode__Syms.h obj_dir/VVX_decode__ver.d obj_dir/VVX_decode_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_decode.v VX_register_file.v

13
rtl/obj_dir/VVX_decode__verFiles.dat
View File

@@ -1,13 +0,0 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-Wall -cc VX_decode.v VX_register_file.v"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 9277 12889063385 1553149232 0 1553149232 0 "VX_decode.v"
S 726 12889070228 1553138880 0 1553138880 0 "VX_register_file.v"
T 30372 12889070221 1553149234 0 1553149234 0 "obj_dir/VVX_decode.cpp"
T 3820 12889070220 1553149234 0 1553149234 0 "obj_dir/VVX_decode.h"
T 1476 12889070223 1553149234 0 1553149234 0 "obj_dir/VVX_decode.mk"
T 545 12889070219 1553149234 0 1553149234 0 "obj_dir/VVX_decode__Syms.cpp"
T 732 12889070218 1553149234 0 1553149234 0 "obj_dir/VVX_decode__Syms.h"
T 319 12889070301 1553149234 0 1553149234 0 "obj_dir/VVX_decode__ver.d"
T 0 0 1553149234 0 1553149234 0 "obj_dir/VVX_decode__verFiles.dat"
T 1168 12889070222 1553149234 0 1553149234 0 "obj_dir/VVX_decode_classes.mk"

38
rtl/obj_dir/VVX_decode_classes.mk
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@@ -1,38 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See VVX_decode.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
VVX_decode \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
VVX_decode__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

200
rtl/obj_dir/VVX_register_file.cpp
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@@ -1,200 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VVX_register_file.h for the primary calling header
#include "VVX_register_file.h"
#include "VVX_register_file__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(VVX_register_file) {
VVX_register_file__Syms* __restrict vlSymsp = __VlSymsp = new VVX_register_file__Syms(this, name());
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void VVX_register_file::__Vconfigure(VVX_register_file__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
VVX_register_file::~VVX_register_file() {
delete __VlSymsp; __VlSymsp=NULL;
}
//--------------------
void VVX_register_file::eval() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_register_file::eval\n"); );
VVX_register_file__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
#ifdef VL_DEBUG
// Debug assertions
_eval_debug_assertions();
#endif // VL_DEBUG
// Initialize
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
void VVX_register_file::_eval_initial_loop(VVX_register_file__Syms* __restrict vlSymsp) {
vlSymsp->__Vm_didInit = true;
_eval_initial(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
_eval_settle(vlSymsp);
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
//--------------------
// Internal Methods
VL_INLINE_OPT void VVX_register_file::_sequent__TOP__1(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_sequent__TOP__1\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Variables
// Begin mtask footprint all:
VL_SIG8(__Vdlyvdim0__VX_register_file__DOT__registers__v0,4,0);
VL_SIG8(__Vdlyvset__VX_register_file__DOT__registers__v0,0,0);
VL_SIG(__Vdlyvval__VX_register_file__DOT__registers__v0,31,0);
// Body
__Vdlyvset__VX_register_file__DOT__registers__v0 = 0U;
// ALWAYS at VX_register_file.v:30
if (((IData)(vlTOPp->in_write_register) & (0U != (IData)(vlTOPp->in_rd)))) {
__Vdlyvval__VX_register_file__DOT__registers__v0
= vlTOPp->in_data;
__Vdlyvset__VX_register_file__DOT__registers__v0 = 1U;
__Vdlyvdim0__VX_register_file__DOT__registers__v0
= vlTOPp->in_rd;
}
// ALWAYSPOST at VX_register_file.v:32
if (__Vdlyvset__VX_register_file__DOT__registers__v0) {
vlTOPp->VX_register_file__DOT__registers[__Vdlyvdim0__VX_register_file__DOT__registers__v0]
= __Vdlyvval__VX_register_file__DOT__registers__v0;
}
}
VL_INLINE_OPT void VVX_register_file::_settle__TOP__2(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_settle__TOP__2\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->out_src1_data = vlTOPp->VX_register_file__DOT__registers
[vlTOPp->in_src1];
vlTOPp->out_src2_data = vlTOPp->VX_register_file__DOT__registers
[vlTOPp->in_src2];
}
void VVX_register_file::_eval(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
vlTOPp->_sequent__TOP__1(vlSymsp);
}
vlTOPp->_settle__TOP__2(vlSymsp);
// Final
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}
void VVX_register_file::_eval_initial(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_initial\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
}
void VVX_register_file::final() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::final\n"); );
// Variables
VVX_register_file__Syms* __restrict vlSymsp = this->__VlSymsp;
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void VVX_register_file::_eval_settle(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_settle\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->_settle__TOP__2(vlSymsp);
}
VL_INLINE_OPT QData VVX_register_file::_change_request(VVX_register_file__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_change_request\n"); );
VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// Change detection
QData __req = false; // Logically a bool
return __req;
}
#ifdef VL_DEBUG
void VVX_register_file::_eval_debug_assertions() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_eval_debug_assertions\n"); );
// Body
if (VL_UNLIKELY((clk & 0xfeU))) {
Verilated::overWidthError("clk");}
if (VL_UNLIKELY((in_write_register & 0xfeU))) {
Verilated::overWidthError("in_write_register");}
if (VL_UNLIKELY((in_rd & 0xe0U))) {
Verilated::overWidthError("in_rd");}
if (VL_UNLIKELY((in_src1 & 0xe0U))) {
Verilated::overWidthError("in_src1");}
if (VL_UNLIKELY((in_src2 & 0xe0U))) {
Verilated::overWidthError("in_src2");}
}
#endif // VL_DEBUG
void VVX_register_file::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_register_file::_ctor_var_reset\n"); );
// Body
clk = VL_RAND_RESET_I(1);
in_write_register = VL_RAND_RESET_I(1);
in_rd = VL_RAND_RESET_I(5);
in_data = VL_RAND_RESET_I(32);
in_src1 = VL_RAND_RESET_I(5);
in_src2 = VL_RAND_RESET_I(5);
out_src1_data = VL_RAND_RESET_I(32);
out_src2_data = VL_RAND_RESET_I(32);
{ int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
VX_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
}}
}

88
rtl/obj_dir/VVX_register_file.h
View File

@@ -1,88 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _VVX_register_file_H_
#define _VVX_register_file_H_
#include "verilated.h"
class VVX_register_file__Syms;
//----------
VL_MODULE(VVX_register_file) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
// Begin mtask footprint all:
VL_IN8(clk,0,0);
VL_IN8(in_write_register,0,0);
VL_IN8(in_rd,4,0);
VL_IN8(in_src1,4,0);
VL_IN8(in_src2,4,0);
VL_IN(in_data,31,0);
VL_OUT(out_src1_data,31,0);
VL_OUT(out_src2_data,31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG(VX_register_file__DOT__registers[32],31,0);
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(__Vclklast__TOP__clk,0,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
VVX_register_file__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
VL_UNCOPYABLE(VVX_register_file); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
VVX_register_file(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~VVX_register_file();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(VVX_register_file__Syms* __restrict vlSymsp);
public:
void __Vconfigure(VVX_register_file__Syms* symsp, bool first);
private:
static QData _change_request(VVX_register_file__Syms* __restrict vlSymsp);
void _ctor_var_reset();
public:
static void _eval(VVX_register_file__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(VVX_register_file__Syms* __restrict vlSymsp);
static void _eval_settle(VVX_register_file__Syms* __restrict vlSymsp);
static void _sequent__TOP__1(VVX_register_file__Syms* __restrict vlSymsp);
static void _settle__TOP__2(VVX_register_file__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(128);
#endif // guard

53
rtl/obj_dir/VVX_register_file.mk
View File

@@ -1,53 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f VVX_register_file.mk
default: VVX_register_file__ALL.a
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = VVX_register_file
# Module prefix (from --prefix)
VM_MODPREFIX = VVX_register_file
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
### Default rules...
# Include list of all generated classes
include VVX_register_file_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
# Verilated -*- Makefile -*-

19
rtl/obj_dir/VVX_register_file__Syms.cpp
View File

@@ -1,19 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "VVX_register_file__Syms.h"
#include "VVX_register_file.h"
// FUNCTIONS
VVX_register_file__Syms::VVX_register_file__Syms(VVX_register_file* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
}

34
rtl/obj_dir/VVX_register_file__Syms.h
View File

@@ -1,34 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header
#ifndef _VVX_register_file__Syms_H_
#define _VVX_register_file__Syms_H_
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "VVX_register_file.h"
// SYMS CLASS
class VVX_register_file__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_didInit;
// SUBCELL STATE
VVX_register_file* TOPp;
// CREATORS
VVX_register_file__Syms(VVX_register_file* topp, const char* namep);
~VVX_register_file__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
} VL_ATTR_ALIGNED(64);
#endif // guard

1
rtl/obj_dir/VVX_register_file__ver.d
View File

@@ -1 +0,0 @@
obj_dir/VVX_register_file.cpp obj_dir/VVX_register_file.h obj_dir/VVX_register_file.mk obj_dir/VVX_register_file__Syms.cpp obj_dir/VVX_register_file__Syms.h obj_dir/VVX_register_file__ver.d obj_dir/VVX_register_file_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_register_file.v

12
rtl/obj_dir/VVX_register_file__verFiles.dat
View File

@@ -1,12 +0,0 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-Wall -cc VX_register_file.v"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 726 12889070228 1553138880 0 1553138880 0 "VX_register_file.v"
T 7234 12889070262 1553138884 0 1553138884 0 "obj_dir/VVX_register_file.cpp"
T 2914 12889070261 1553138884 0 1553138884 0 "obj_dir/VVX_register_file.h"
T 1511 12889070264 1553138884 0 1553138884 0 "obj_dir/VVX_register_file.mk"
T 580 12889070260 1553138884 0 1553138884 0 "obj_dir/VVX_register_file__Syms.cpp"
T 781 12889070259 1553138884 0 1553138884 0 "obj_dir/VVX_register_file__Syms.h"
T 356 12889070265 1553138884 0 1553138884 0 "obj_dir/VVX_register_file__ver.d"
T 0 0 1553138884 0 1553138884 0 "obj_dir/VVX_register_file__verFiles.dat"
T 1189 12889070263 1553138884 0 1553138884 0 "obj_dir/VVX_register_file_classes.mk"

38
rtl/obj_dir/VVX_register_file_classes.mk
View File

@@ -1,38 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See VVX_register_file.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
VVX_register_file \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
VVX_register_file__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

BIN
rtl/obj_dir/Vvortex
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Binary file not shown.

1838
rtl/obj_dir/Vvortex.cpp
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149
rtl/obj_dir/Vvortex.h
View File

@@ -5,16 +5,16 @@
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _Vvortex_H_
#define _Vvortex_H_
#ifndef _VVortex_H_
#define _VVortex_H_
#include "verilated_heavy.h"
#include "verilated.h"
class Vvortex__Syms;
class VVortex__Syms;
//----------
VL_MODULE(Vvortex) {
VL_MODULE(VVortex) {
public:
// PORTS
@@ -23,24 +23,103 @@ VL_MODULE(Vvortex) {
// Begin mtask footprint all:
VL_IN8(clk,0,0);
VL_IN8(reset,0,0);
VL_OUT8(fe_delay,0,0);
VL_OUT8(out_cache_driver_in_mem_read,2,0);
VL_OUT8(out_cache_driver_in_mem_write,2,0);
VL_IN(fe_instruction,31,0);
VL_IN(in_cache_driver_out_data,31,0);
VL_OUT(curr_PC,31,0);
VL_OUT(de_instruction,31,0);
VL_OUT(out_cache_driver_in_address,31,0);
VL_OUT(out_cache_driver_in_data,31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(vortex__DOT__vx_fetch__DOT__stall_reg,0,0);
VL_SIG8(vortex__DOT__vx_fetch__DOT__delay_reg,0,0);
VL_SIG8(vortex__DOT__vx_fetch__DOT__state,4,0);
VL_SIG8(vortex__DOT__vx_fetch__DOT__prev_debug,0,0);
VL_SIG(vortex__DOT__vx_fetch__DOT__old,31,0);
VL_SIG(vortex__DOT__vx_fetch__DOT__real_PC,31,0);
VL_SIG(vortex__DOT__vx_fetch__DOT__JAL_reg,31,0);
VL_SIG(vortex__DOT__vx_fetch__DOT__BR_reg,31,0);
VL_SIG(vortex__DOT__vx_fetch__DOT__PC_to_use,31,0);
VL_SIG(vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
// Anonymous structures to workaround compiler member-count bugs
struct {
// Begin mtask footprint all:
VL_SIG8(Vortex__DOT__decode_branch_type,2,0);
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall_reg,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__delay_reg,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__state,4,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,3,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rs2_src,0,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_read,2,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_write,2,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__branch_type,2,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__jal,0,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid,0,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__stalling,0,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__rd,4,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__wb,1,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_read,2,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_write,2,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__branch_type,2,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__jal,0,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid,0,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__rd,4,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__wb,1,0);
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd,0,0);
VL_SIG16(Vortex__DOT__decode_csr_address,11,0);
VL_SIG16(Vortex__DOT__vx_decode__DOT__alu_tempp,11,0);
VL_SIG16(Vortex__DOT__vx_d_e_reg__DOT__csr_address,11,0);
VL_SIG16(Vortex__DOT__vx_e_m_reg__DOT__csr_address,11,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
VL_SIG(Vortex__DOT__decode_rd1,31,0);
VL_SIG(Vortex__DOT__decode_itype_immed,31,0);
VL_SIG(Vortex__DOT__execute_alu_result,31,0);
VL_SIG(Vortex__DOT__memory_branch_dest,31,0);
VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__old,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__JAL_reg,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__BR_reg,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__PC_to_use,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd1,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd2,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT__ALU_in2,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__rd2,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result,31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result,31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[32],31,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
};
// LOCAL VARIABLES
// Internals; generally not touched by application code
@@ -50,21 +129,21 @@ VL_MODULE(Vvortex) {
// INTERNAL VARIABLES
// Internals; generally not touched by application code
Vvortex__Syms* __VlSymsp; // Symbol table
VVortex__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
VL_UNCOPYABLE(Vvortex); ///< Copying not allowed
VL_UNCOPYABLE(VVortex); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
Vvortex(const char* name="TOP");
VVortex(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~Vvortex();
~VVortex();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
@@ -74,27 +153,29 @@ VL_MODULE(Vvortex) {
// INTERNAL METHODS
private:
static void _eval_initial_loop(Vvortex__Syms* __restrict vlSymsp);
static void _eval_initial_loop(VVortex__Syms* __restrict vlSymsp);
public:
void __Vconfigure(Vvortex__Syms* symsp, bool first);
void __Vconfigure(VVortex__Syms* symsp, bool first);
private:
static QData _change_request(VVortex__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__6(VVortex__Syms* __restrict vlSymsp);
private:
static QData _change_request(Vvortex__Syms* __restrict vlSymsp);
void _ctor_var_reset();
public:
static void _eval(Vvortex__Syms* __restrict vlSymsp);
static void _eval(VVortex__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(Vvortex__Syms* __restrict vlSymsp);
static void _eval_settle(Vvortex__Syms* __restrict vlSymsp);
static void _initial__TOP__4(Vvortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__2(Vvortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__3(Vvortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__5(Vvortex__Syms* __restrict vlSymsp);
static void _settle__TOP__1(Vvortex__Syms* __restrict vlSymsp);
static void _settle__TOP__6(Vvortex__Syms* __restrict vlSymsp);
static void _eval_initial(VVortex__Syms* __restrict vlSymsp);
static void _eval_settle(VVortex__Syms* __restrict vlSymsp);
static void _initial__TOP__3(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__1(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__4(VVortex__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(128);
#endif // guard

12
rtl/obj_dir/Vvortex.mk
View File

@@ -2,9 +2,9 @@
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vvortex.mk
# make -f VVortex.mk
default: Vvortex
default: VVortex
### Constants...
# Perl executable (from $PERL)
@@ -28,9 +28,9 @@ VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vvortex
VM_PREFIX = VVortex
# Module prefix (from --prefix)
VM_MODPREFIX = Vvortex
VM_MODPREFIX = VVortex
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
@@ -48,7 +48,7 @@ VM_USER_DIR = \
### Default rules...
# Include list of all generated classes
include Vvortex_classes.mk
include VVortex_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
@@ -59,7 +59,7 @@ test_bench.o: test_bench.cpp
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
Vvortex: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
VVortex: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS)

BIN
rtl/obj_dir/Vvortex__ALL.a
View File

Binary file not shown.

2
rtl/obj_dir/Vvortex__ALLcls.cpp
View File

@@ -1,3 +1,3 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vvortex.cpp"
#include "VVortex.cpp"

5
rtl/obj_dir/Vvortex__ALLcls.d
View File

@@ -1,5 +1,4 @@
Vvortex__ALLcls.o: Vvortex__ALLcls.cpp Vvortex.cpp Vvortex.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
Vvortex__Syms.h
VVortex__Syms.h

2
rtl/obj_dir/Vvortex__ALLsup.cpp
View File

@@ -1,3 +1,3 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vvortex__Syms.cpp"
#include "VVortex__Syms.cpp"

5
rtl/obj_dir/Vvortex__ALLsup.d
View File

@@ -1,5 +1,4 @@
Vvortex__ALLsup.o: Vvortex__ALLsup.cpp Vvortex__Syms.cpp Vvortex__Syms.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
Vvortex.h
VVortex.h

6
rtl/obj_dir/Vvortex__Syms.cpp
View File

@@ -1,11 +1,11 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vvortex__Syms.h"
#include "Vvortex.h"
#include "VVortex__Syms.h"
#include "VVortex.h"
// FUNCTIONS
Vvortex__Syms::Vvortex__Syms(Vvortex* topp, const char* namep)
VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)

16
rtl/obj_dir/Vvortex__Syms.h
View File

@@ -3,16 +3,16 @@
//
// Internal details; most calling programs do not need this header
#ifndef _Vvortex__Syms_H_
#define _Vvortex__Syms_H_
#ifndef _VVortex__Syms_H_
#define _VVortex__Syms_H_
#include "verilated_heavy.h"
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "Vvortex.h"
#include "VVortex.h"
// SYMS CLASS
class Vvortex__Syms : public VerilatedSyms {
class VVortex__Syms : public VerilatedSyms {
public:
// LOCAL STATE
@@ -20,11 +20,11 @@ class Vvortex__Syms : public VerilatedSyms {
bool __Vm_didInit;
// SUBCELL STATE
Vvortex* TOPp;
VVortex* TOPp;
// CREATORS
Vvortex__Syms(Vvortex* topp, const char* namep);
~Vvortex__Syms() {}
VVortex__Syms(VVortex* topp, const char* namep);
~VVortex__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }

2
rtl/obj_dir/Vvortex__ver.d
View File

@@ -1 +1 @@
obj_dir/Vvortex.cpp obj_dir/Vvortex.h obj_dir/Vvortex.mk obj_dir/Vvortex__Syms.cpp obj_dir/Vvortex__Syms.h obj_dir/Vvortex__ver.d obj_dir/Vvortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_f_d_reg.v VX_fetch.v vortex.v
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v

33
rtl/obj_dir/Vvortex__verFiles.dat
View File

@@ -1,14 +1,25 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-Wall -cc vortex.v VX_f_d_reg.v VX_fetch.v --exe test_bench.cpp"
C "-Wall -cc Vortex.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 960 12889050060 1553112201 0 1553112201 0 "VX_f_d_reg.v"
S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v"
S 4626 12889079539 1553190875 0 1553190875 0 "VX_d_e_reg.v"
S 8412 12889063385 1553211412 0 1553211412 0 "VX_decode.v"
S 1351 12889079483 1553200040 0 1553200040 0 "VX_define.v"
S 3644 12889083963 1553196174 0 1553196174 0 "VX_e_m_reg.v"
S 4603 12889081819 1553208546 0 1553208546 0 "VX_execute.v"
S 969 12889050060 1553223828 0 1553223828 0 "VX_f_d_reg.v"
S 3337 12889047675 1553112414 0 1553112414 0 "VX_fetch.v"
T 11853 12889064939 1553112478 0 1553112478 0 "obj_dir/Vvortex.cpp"
T 3513 12889064938 1553112478 0 1553112478 0 "obj_dir/Vvortex.h"
T 1800 12889064941 1553112478 0 1553112478 0 "obj_dir/Vvortex.mk"
T 530 12889064937 1553112478 0 1553112478 0 "obj_dir/Vvortex__Syms.cpp"
T 717 12889064936 1553112478 0 1553112478 0 "obj_dir/Vvortex__Syms.h"
T 300 12889064942 1553112478 0 1553112478 0 "obj_dir/Vvortex__ver.d"
T 0 0 1553112478 0 1553112478 0 "obj_dir/Vvortex__verFiles.dat"
T 1159 12889064940 1553112478 0 1553112478 0 "obj_dir/Vvortex_classes.mk"
S 1826 12889050092 1553109861 0 1553109861 0 "vortex.v"
S 4771 12889086478 1553200651 0 1553200651 0 "VX_forwarding.v"
S 1578 12889085814 1553211072 0 1553211072 0 "VX_m_w_reg.v"
S 2315 12889084513 1553197906 0 1553197906 0 "VX_memory.v"
S 726 12889070228 1553188094 0 1553188094 0 "VX_register_file.v"
S 597 12889086287 1553199222 0 1553199222 0 "VX_writeback.v"
S 12863 12889050092 1553211358 0 1553211358 0 "Vortex.v"
T 77457 12889096617 1553223839 0 1553223839 0 "obj_dir/VVortex.cpp"
T 7575 12889096616 1553223839 0 1553223839 0 "obj_dir/VVortex.h"
T 1800 12889096619 1553223839 0 1553223839 0 "obj_dir/VVortex.mk"
T 530 12889096615 1553223839 0 1553223839 0 "obj_dir/VVortex__Syms.cpp"
T 711 12889096614 1553223839 0 1553223839 0 "obj_dir/VVortex__Syms.h"
T 455 12889096620 1553223839 0 1553223839 0 "obj_dir/VVortex__ver.d"
T 0 0 1553223839 0 1553223839 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889096618 1553223839 0 1553223839 0 "obj_dir/VVortex_classes.mk"

6
rtl/obj_dir/Vvortex_classes.mk
View File

@@ -2,7 +2,7 @@
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vvortex.mk for the caller.
# See VVortex.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
@@ -15,7 +15,7 @@ VM_TRACE = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vvortex \
VVortex \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
@@ -25,7 +25,7 @@ VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vvortex__Syms \
VVortex__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \

4
rtl/obj_dir/test_bench.d
View File

@@ -1,4 +1,4 @@
test_bench.o: ../test_bench.cpp Vvortex.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \
VVortex.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h