fixed no shared memory bug, fixed cache debug log
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8
hw/rtl/cache/VX_shared_mem.v
vendored
8
hw/rtl/cache/VX_shared_mem.v
vendored
@@ -264,11 +264,11 @@ module VX_shared_mem #(
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
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assign {debug_pc_st0[i], debug_wid_st0[i]} = per_bank_core_req_tag_unqual[i][CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
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assign {debug_pc_st1[i], debug_wid_st1[i]} = per_bank_core_req_tag[i][CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
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assign {debug_wid_st0[i], debug_pc_st0[i]} = per_bank_core_req_tag_unqual[i][`CACHE_REQ_INFO_RNG];
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assign {debug_wid_st1[i], debug_pc_st1[i]} = per_bank_core_req_tag[i][`CACHE_REQ_INFO_RNG];
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end else begin
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assign {debug_pc_st0[i], debug_wid_st0[i]} = 0;
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assign {debug_pc_st1[i], debug_wid_st1[i]} = 0;
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assign {debug_wid_st0[i], debug_pc_st0[i]} = 0;
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assign {debug_wid_st1[i], debug_pc_st1[i]} = 0;
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end
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end
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`endif
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