bram block optimization
This commit is contained in:
4
hw/rtl/cache/VX_data_access.v
vendored
4
hw/rtl/cache/VX_data_access.v
vendored
@@ -70,9 +70,7 @@ module VX_data_access #(
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) data_store (
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.clk(clk),
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.addr(line_addr),
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.wren(writeen),
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.byteen(byte_enable),
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.rden(1'b1),
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.wren({BYTEENW{writeen}} & byte_enable),
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.din(wdata),
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.dout(rdata)
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);
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2
hw/rtl/cache/VX_miss_resrv.v
vendored
2
hw/rtl/cache/VX_miss_resrv.v
vendored
@@ -180,8 +180,6 @@ module VX_miss_resrv #(
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.waddr (allocate_id_r),
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.raddr (dequeue_id_r),
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.wren (allocate_valid),
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.byteen (1'b1),
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.rden (1'b1),
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.din (allocate_data),
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.dout (dequeue_data)
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);
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6
hw/rtl/cache/VX_tag_access.v
vendored
6
hw/rtl/cache/VX_tag_access.v
vendored
@@ -53,16 +53,14 @@ module VX_tag_access #(
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) tag_store (
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.clk(clk),
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.addr(line_addr),
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.wren(fill && ~stall),
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.byteen(1'b1),
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.rden(1'b1),
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.wren(fill),
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.din({!is_flush, line_tag}),
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.dout({read_valid, read_tag})
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);
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assign tag_match = read_valid && (line_tag == read_tag);
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`RUNTIME_ASSERT((~(fill && ~stall && ~is_flush) || ~tag_match), ("%t: redundant fill - addr=%0h, tag_id=%0h", $time, `LINE_TO_BYTE_ADDR(addr, BANK_ID), read_tag))
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`UNUSED_VAR (stall)
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`ifdef DBG_PRINT_CACHE_TAG
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always @(posedge clk) begin
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