bram block optimization

This commit is contained in:
Blaise Tine
2021-08-13 19:31:55 -07:00
parent 4336dcb2a8
commit 646371f9e9
9 changed files with 56 additions and 110 deletions

View File

@@ -70,9 +70,7 @@ module VX_data_access #(
) data_store (
.clk(clk),
.addr(line_addr),
.wren(writeen),
.byteen(byte_enable),
.rden(1'b1),
.wren({BYTEENW{writeen}} & byte_enable),
.din(wdata),
.dout(rdata)
);

View File

@@ -180,8 +180,6 @@ module VX_miss_resrv #(
.waddr (allocate_id_r),
.raddr (dequeue_id_r),
.wren (allocate_valid),
.byteen (1'b1),
.rden (1'b1),
.din (allocate_data),
.dout (dequeue_data)
);

View File

@@ -53,16 +53,14 @@ module VX_tag_access #(
) tag_store (
.clk(clk),
.addr(line_addr),
.wren(fill && ~stall),
.byteen(1'b1),
.rden(1'b1),
.wren(fill),
.din({!is_flush, line_tag}),
.dout({read_valid, read_tag})
);
assign tag_match = read_valid && (line_tag == read_tag);
`RUNTIME_ASSERT((~(fill && ~stall && ~is_flush) || ~tag_match), ("%t: redundant fill - addr=%0h, tag_id=%0h", $time, `LINE_TO_BYTE_ADDR(addr, BANK_ID), read_tag))
`UNUSED_VAR (stall)
`ifdef DBG_PRINT_CACHE_TAG
always @(posedge clk) begin