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RTL code refactoring

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Blaise Tine
2020-04-20 07:24:20 -04:00
parent 58850a2fe8
commit 62c1c3fdbb
8 changed files with 145 additions and 145 deletions
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14
hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
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@@ -8,17 +8,17 @@ interface VX_gpu_dcache_rsp_if #(
) ();
// Core response
wire [NUM_REQUESTS-1:0] core_wb_valid;
wire [NUM_REQUESTS-1:0] core_rsp_valid;
`IGNORE_WARNINGS_BEGIN
wire [4:0] core_wb_req_rd;
wire [1:0] core_wb_req_wb;
wire [4:0] core_rsp_req_rd;
wire [1:0] core_rsp_req_wb;
`IGNORE_WARNINGS_END
wire [NUM_REQUESTS-1:0][31:0] core_wb_pc;
wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata;
wire core_no_wb_slot;
wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc;
wire [NUM_REQUESTS-1:0][31:0] core_rsp_readdata;
wire core_rsp_ready;
// Core response meta data
wire [`NW_BITS-1:0] core_wb_warp_num;
wire [`NW_BITS-1:0] core_rsp_warp_num;
endinterface