wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'refs/remotes/origin/master'

Browse Source
This commit is contained in:
Euna Kim
2019-11-23 22:25:45 -05:00
parent 715dc3089e cec065b6fd
commit 62ab6b3e98
137 changed files with 2472848 additions and 2586571 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
simX/Makefile
View File

@@ -1,7 +1,7 @@
################################################################################
# HARPtools by Chad D. Kersey, Summer 2011 #
################################################################################
CXXFLAGS ?= -std=c++11 -fPIC -O3 # -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
CXXFLAGS ?= -std=c++11 -fPIC -O3 -g # -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
LIB_OBJS=simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp

133
simX/core.cpp
View File

@@ -46,7 +46,8 @@
trace_inst.vd = -1; \
trace_inst.is_lw = false; \
trace_inst.is_sw = false; \
trace_inst.mem_addresses = new unsigned[a.getNThds()]; \
if (trace_inst.mem_addresses != NULL) free(trace_inst.mem_addresses); \
trace_inst.mem_addresses = (unsigned *) malloc(32 * sizeof(unsigned)); \
for (int tid = 0; tid < a.getNThds(); tid++) trace_inst.mem_addresses[tid] = 0xdeadbeef; \
trace_inst.mem_stall_cycles = 0; \
trace_inst.fetch_stall_cycles = 0; \
@@ -79,19 +80,19 @@ using namespace std;
void printTrace(trace_inst_t * trace, const char * stage_name)
{
cout << "********************************** " << stage_name << " *********************************\n";
cout << "valid: " << trace->valid_inst << '\n';
cout << "PC: " << hex << trace->pc << dec << '\n';
cout << "wid: " << trace->wid << '\n';
cout << "rd: " << trace->rd << "\trs1: " << trace->rs1 << "\trs2: " << trace->rs2 << '\n';
cout << "is_lw: " << trace->is_lw << '\n';
cout << "is_sw: " << trace->is_sw << '\n';
cout << "fetch_stall_cycles: " << trace->fetch_stall_cycles << '\n';
cout << "mem_stall_cycles: " << trace->mem_stall_cycles << '\n';
D(3, "********************************** " << stage_name << " *********************************");
D(3, "valid: " << trace->valid_inst);
D(3, "PC: " << hex << trace->pc << dec);
D(3, "wid: " << trace->wid);
D(3, "rd: " << trace->rd << "\trs1: " << trace->rs1 << "\trs2: " << trace->rs2);
D(3, "is_lw: " << trace->is_lw);
D(3, "is_sw: " << trace->is_sw);
D(3, "fetch_stall_cycles: " << trace->fetch_stall_cycles);
D(3, "mem_stall_cycles: " << trace->mem_stall_cycles);
cout << "stall_warp: " << trace->stall_warp << '\n';
cout << "wspawn: " << trace->wspawn << '\n';
cout << "stalled: " << trace->stalled << '\n';
D(3, "stall_warp: " << trace->stall_warp);
D(3, "wspawn: " << trace->wspawn);
D(3, "stalled: " << trace->stalled);
}
#ifdef EMU_INSTRUMENTATION
@@ -105,7 +106,7 @@ void Harp::reg_doWrite(Word cpuId, Word regNum) {
#endif
Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
a(a), iDec(d), mem(mem), steps(4)
a(a), iDec(d), mem(mem), steps(4), num_cycles(0), num_instructions(0)
{
release_warp = false;
foundSchedule = true;
@@ -133,9 +134,9 @@ Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
cache_simulator = new Vcache_simX;
m_trace = new VerilatedVcdC;
cache_simulator->trace(m_trace, 99);
m_trace->open("simXtrace.vcd");
// m_trace = new VerilatedVcdC;
// cache_simulator->trace(m_trace, 99);
// m_trace->open("simXtrace.vcd");
cache_simulator->reset = 1;
cache_simulator->clk = 0;
@@ -161,38 +162,50 @@ bool Core::interrupt(Word r0) {
void Core::step()
{
cout << "\n\n\n------------------------------------------------------\n";
D(3, "\n\n\n------------------------------------------------------");
D(3, "Started core::step" << flush);
steps++;
cout << "CYCLE: " << steps << '\n';
this->num_cycles++;
D(3, "CYCLE: " << this->num_cycles);
cout << "Stalled Warps:\n";
D(3, "Stalled Warps:");
for (int widd = 0; widd < a.getNWarps(); widd++)
{
cout << stallWarp[widd] << " ";
D(3, stallWarp[widd] << " ");
}
cout << '\n';
// cout << "Rename table\n";
// for (int regii = 0; regii < 32; regii++)
// {
// cout << regii << ": " << renameTable[0][regii] << '\n';
// }
cout << '\n';
// cout << '\n' << flush;
// cout << "About to call writeback" << endl;
this->writeback();
// cout << "About to call load_store" << endl;
this->load_store();
// cout << "About to call execute_unit" << endl;
this->execute_unit();
// cout << "About to call scheduler" << endl;
this->scheduler();
// cout << "About to call decode" << endl;
this->decode();
// D(3, "About to call fetch" << flush);
this->fetch();
// D(3, "Finished fetch" << flush);
if (release_warp)
{
release_warp = false;
stallWarp[release_warp_num] = false;
}
D(3, "released warp" << flush);
D(3, "Finished core::step" << flush);
}
void Core::getCacheDelays(trace_inst_t * trace_inst)
@@ -238,7 +251,7 @@ void Core::getCacheDelays(trace_inst_t * trace_inst)
cache_simulator->clk = 1;
cache_simulator->eval();
m_trace->dump(2*curr_cycle);
// m_trace->dump(2*curr_cycle);
cache_simulator->in_icache_pc_addr = trace_inst->pc;
cache_simulator->in_icache_valid_pc_addr = 1;
@@ -254,7 +267,7 @@ void Core::getCacheDelays(trace_inst_t * trace_inst)
// DCache end
cache_simulator->clk = 0;
cache_simulator->eval();
m_trace->dump(2*curr_cycle+1);
// m_trace->dump(2*curr_cycle+1);
curr_cycle++;
@@ -296,7 +309,7 @@ void Core::getCacheDelays(trace_inst_t * trace_inst)
cache_simulator->clk = 1;
cache_simulator->eval();
m_trace->dump(2*curr_cycle);
// m_trace->dump(2*curr_cycle);
//////// Feed input
if (cache_simulator->out_icache_stall)
@@ -331,7 +344,7 @@ void Core::getCacheDelays(trace_inst_t * trace_inst)
cache_simulator->clk = 0;
cache_simulator->eval();
m_trace->dump(2*curr_cycle+1);
// m_trace->dump(2*curr_cycle+1);
curr_cycle++;
@@ -378,9 +391,9 @@ void Core::warpScheduler()
void Core::fetch()
{
#ifdef PRINT_ACTIVE_THREADS
cout << endl << "Threads:";
#endif
// #ifdef PRINT_ACTIVE_THREADS
D(3, "Threads:");
// #endif
// D(-1, "Found schedule: " << foundSchedule);
@@ -395,16 +408,22 @@ void Core::fetch()
if (foundSchedule)
{
D(3, "Core step stepping warp " << schedule_w << '[' << w[schedule_w].activeThreads << ']');
this->num_instructions = this->num_instructions + w[schedule_w].activeThreads;
// this->num_instructions++;
w[schedule_w].step(&inst_in_fetch);
D(3, "Now " << w[schedule_w].activeThreads << " active threads in " << schedule_w);
D(3, "Now " << w[schedule_w].activeThreads << " active threads in " << schedule_w << flush);
this->getCacheDelays(&inst_in_fetch);
// this->getCacheDelays(&inst_in_fetch);
D(3, "Got cache delays" << flush);
if (inst_in_fetch.stall_warp)
{
stallWarp[inst_in_fetch.wid] = true;
}
D(3, "staled warps\n" << flush);
}
D(3, "About to schedule warp\n" << flush);
warpScheduler();
D(3, "Scheduled warp" << flush);
}
}
else
@@ -413,21 +432,33 @@ void Core::fetch()
if (inst_in_fetch.fetch_stall_cycles > 0) inst_in_fetch.fetch_stall_cycles--;
}
D(3, "Printing trace" << flush);
printTrace(&inst_in_fetch, "Fetch");
D(3, "printed trace" << flush);
// #ifdef PRINT_ACTIVE_THREADS
D(3, "About to print active threads" << flush << "\n");
for (unsigned j = 0; j < w[schedule_w].tmask.size(); ++j) {
if (w[schedule_w].activeThreads > j && w[schedule_w].tmask[j]) cout << " 1";
else cout << " 0";
if (j != w[schedule_w].tmask.size()-1 || schedule_w != w.size()-1) cout << ',';
if (w[schedule_w].activeThreads > j && w[schedule_w].tmask[j])
{
D(3, " 1");
}
else
{
D(3, " 0");
}
if (j != w[schedule_w].tmask.size()-1 || schedule_w != w.size()-1)
{
D(3, ',');
}
}
D(3, "\nPrinted active threads" << flush);
// #endif
#ifdef PRINT_ACTIVE_THREADS
cout << endl;
#endif
// #ifdef PRINT_ACTIVE_THREADS
// #endif
}
void Core::decode()
@@ -522,7 +553,7 @@ void Core::load_store()
void Core::execute_unit()
{
// cout << "$$$$$$$$$$$$$$$$$$$ EXE START\n";
D(3, "$$$$$$$$$$$$$$$$$$$ EXE START\n" << flush);
bool do_nothing = false;
// EXEC is always not busy
if (inst_in_scheduler.is_lw || inst_in_scheduler.is_sw)
@@ -546,6 +577,7 @@ void Core::execute_unit()
// cout << "Rename RS2: " << inst_in_scheduler.rs1 << " is " << renameTable[inst_in_scheduler.wid][inst_in_scheduler.rs2] << " wid: " << inst_in_scheduler.wid << '\n';
}
// cout << "About to check vs*\n" << flush;
if(inst_in_scheduler.vs1 > 0)
{
scheduler_srcs_ready = scheduler_srcs_ready && vecRenameTable[inst_in_scheduler.vs1];
@@ -554,6 +586,7 @@ void Core::execute_unit()
{
scheduler_srcs_ready = scheduler_srcs_ready && vecRenameTable[inst_in_scheduler.vs2];
}
// cout << "Finished sources\n" << flush;
if (scheduler_srcs_ready)
{
@@ -561,15 +594,19 @@ void Core::execute_unit()
// cout << "rename setting rd: " << inst_in_scheduler.rd << " to not useabel wid: " << inst_in_scheduler.wid << '\n';
renameTable[inst_in_scheduler.wid][inst_in_scheduler.rd] = false;
}
// cout << "About to check vector wb: " << inst_in_scheduler.vd << "\n" << flush;
if(inst_in_scheduler.vd != -1) {
vecRenameTable[inst_in_scheduler.vd] = false;
}
// cout << "Finished wb checking" << "\n" << flush;
CPY_TRACE(inst_in_exe, inst_in_scheduler);
INIT_TRACE(inst_in_scheduler);
// cout << "Finished trace copying and clearning" << "\n" << flush;
}
else
{
cout << "&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY\n";
D(3, "&&&&&&&&&&&&&&&&&&&&&&&& EXECUTE SRCS NOT READY");
inst_in_scheduler.stalled = true;
// INIT_TRACE(inst_in_exe);
do_nothing = true;
@@ -583,6 +620,7 @@ void Core::execute_unit()
//printTrace(&inst_in_exe, "execute_unit");
// INIT_TRACE(inst_in_exe);
D(3, "EXECUTE END" << flush);
}
void Core::writeback()
@@ -623,7 +661,7 @@ void Core::writeback()
{
if (serviced_exe)
{
cout << "$$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used\n";
D(3, "$$$$$$$$$$$$$$$$$$$$ Stalling LSU because EXE is being used");
inst_in_lsu.stalled = true;
}
else
@@ -652,7 +690,7 @@ bool Core::running() const {
for (unsigned i = 0; i < w.size(); ++i)
if (w[i].running())
{
cout << "Warp ID " << i << " is running\n";
D(3, "Warp ID " << i << " is running");
return true;
}
return false;
@@ -665,7 +703,7 @@ void Core::printStats() const {
cerr << "Total steps: " << steps << endl;
for (unsigned i = 0; i < w.size(); ++i) {
cout << "=== Warp " << i << " ===" << endl;
// cout << "=== Warp " << i << " ===" << endl;
w[i].printStats();
}
}
@@ -715,7 +753,7 @@ void Warp::step(trace_inst_t * trace_inst) {
// ++steps;
D(3, "in step pc=0x" << hex << pc);
cout << "help: in PC: " << hex << pc << dec << '\n';
D(3, "help: in PC: " << hex << pc << dec);
// std::cout << "pc: " << hex << pc << "\n";
@@ -727,8 +765,9 @@ void Warp::step(trace_inst_t * trace_inst) {
bool fetchMore;
fetchMore = false;
unsigned fetchSize(wordSize - (pc+fetchPos)%wordSize);
fetchBuffer.resize(fetchPos + fetchSize);
// unsigned fetchSize(wordSize - (pc+fetchPos)%wordSize);
unsigned fetchSize = 4;
fetchBuffer.resize(fetchSize);
Word fetched = core->mem.fetch(pc + fetchPos, supervisorMode);
writeWord(fetchBuffer, fetchPos, fetchSize, fetched);
decPos = 0;

15
simX/enc.cpp
View File

@@ -104,7 +104,8 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
bool predicated = false;
if (predicated) { inst.setPred((code>>(inst_s-p-1))&pMask); }
printf("CUrrent CODE: %x\n", code);
// printf("CUrrent CODE: %x\n", code);
D(3, "Curr Code: " << hex << code << dec);
Opcode op = (Opcode)((code>>shift_opcode)&opcode_mask);
// std::cout << "opcode: " << op << "\n";
@@ -234,17 +235,17 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
break;
case InstType::V_TYPE:
cout << "Entered here: instr type = vector" << op << endl;
D(3, "Entered here: instr type = vector" << op);
switch(op) {
case Opcode::VSET_ARITH: //TODO: arithmetic ops
inst.setDestReg((code>>shift_rd) & reg_mask);
inst.setSrcReg((code>>shift_rs1) & reg_mask);
func3 = (code>>shift_func3) & func3_mask;
inst.setFunc3 (func3);
cout << "Entered here: instr type = vector" << endl;
D(3, "Entered here: instr type = vector");
if(func3 == 7) {
cout << "Entered here: imm instr";
D(3, "Entered here: imm instr");
inst.setVsetImm(!(code>>shift_vset));
@@ -318,9 +319,9 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
Ref *srcRef = refMap[idx-n/8];
/* Create a new ref tied to this instruction. */
Ref *r = new SimpleRef(srcRef->name, *(Addr*)inst.setSrcImm(),
inst.hasRelImm());
inst.setImmRef(*r);
// Ref *r = new SimpleRef(srcRef->name, *(Addr*)inst.setSrcImm(),
// inst.hasRelImm());
// inst.setImmRef(*r);
}
D(2, "Decoded 0x" << hex << code << " into: " << inst << '\n');

4
simX/include/archdef.h
View File

@@ -23,8 +23,8 @@ namespace Harp {
encChar = 'w';
nRegs = 32;
nPRegs = 0;
nThds = 8;
nWarps = 8;
nThds = 32;
nWarps = 32;
extent = EXT_WARPS;

2
simX/include/core.h
View File

@@ -144,6 +144,8 @@ namespace Harp {
Word interruptEntry;
unsigned long steps;
unsigned long num_cycles;
unsigned long num_instructions;
std::vector<Warp> w;
std::map<Word, std::set<Warp *> > b; // Barriers
int schedule_w;

5
simX/include/debug.h
View File

@@ -5,7 +5,7 @@
#define __DEBUG_H
// #define USE_DEBUG 9
#define USE_DEBUG 3
// #define USE_DEBUG 3
#ifdef USE_DEBUG
#include <iostream>
@@ -21,10 +21,11 @@
#define D_RAW(x) do { \
std::cout << x; \
} while (0)
#else
#define D(lvl, x) do {} while(0)
#define D_RAW(x) do {} while(0)
#endif
#endif

454
simX/instruction.cpp
View File

File diff suppressed because it is too large Load Diff

BIN
simX/obj_dir/Vcache_simX Executable file
View File

Binary file not shown.

208
simX/obj_dir/Vcache_simX.cpp Normal file
View File

@@ -0,0 +1,208 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX) {
Vcache_simX__Syms* __restrict vlSymsp = __VlSymsp = new Vcache_simX__Syms(this, name());
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
VL_CELL (__PVT__v, Vcache_simX_cache_simX);
// Reset internal values
// Reset structure values
clk = VL_RAND_RESET_I(1);
reset = VL_RAND_RESET_I(1);
in_icache_pc_addr = VL_RAND_RESET_I(32);
in_icache_valid_pc_addr = VL_RAND_RESET_I(1);
out_icache_stall = VL_RAND_RESET_I(1);
in_dcache_mem_read = VL_RAND_RESET_I(3);
in_dcache_mem_write = VL_RAND_RESET_I(3);
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
in_dcache_in_valid[__Vi0] = VL_RAND_RESET_I(1);
}}
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
in_dcache_in_address[__Vi0] = VL_RAND_RESET_I(32);
}}
out_dcache_stall = VL_RAND_RESET_I(1);
__Vclklast__TOP__clk = VL_RAND_RESET_I(1);
__Vclklast__TOP__reset = VL_RAND_RESET_I(1);
__Vchglast__TOP__v__dmem_controller__shared_memory__DOT__block_addr = VL_RAND_RESET_I(28);
__Vm_traceActivity = VL_RAND_RESET_I(32);
}
void Vcache_simX::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX::~Vcache_simX() {
delete __VlSymsp; __VlSymsp=NULL;
}
//--------------------
void Vcache_simX::eval() {
Vcache_simX__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Initialize
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
// Evaluate till stable
VL_DEBUG_IF(VL_PRINTF("\n----TOP Evaluate Vcache_simX::eval\n"); );
int __VclockLoop = 0;
QData __Vchange=1;
while (VL_LIKELY(__Vchange)) {
VL_DEBUG_IF(VL_PRINTF(" Clock loop\n"););
vlSymsp->__Vm_activity = true;
_eval(vlSymsp);
__Vchange = _change_request(vlSymsp);
if (++__VclockLoop > 100) vl_fatal(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
}
}
void Vcache_simX::_eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp) {
vlSymsp->__Vm_didInit = true;
_eval_initial(vlSymsp);
vlSymsp->__Vm_activity = true;
int __VclockLoop = 0;
QData __Vchange=1;
while (VL_LIKELY(__Vchange)) {
_eval_settle(vlSymsp);
_eval(vlSymsp);
__Vchange = _change_request(vlSymsp);
if (++__VclockLoop > 100) vl_fatal(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
}
}
//--------------------
// Internal Methods
VL_INLINE_OPT void Vcache_simX::_combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_combo__TOP__1\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v.in_dcache_in_valid[3U] = vlTOPp->in_dcache_in_valid
[3U];
vlSymsp->TOP__v.in_dcache_in_valid[2U] = vlTOPp->in_dcache_in_valid
[2U];
vlSymsp->TOP__v.in_dcache_in_valid[1U] = vlTOPp->in_dcache_in_valid
[1U];
vlSymsp->TOP__v.in_dcache_in_valid[0U] = vlTOPp->in_dcache_in_valid
[0U];
vlSymsp->TOP__v.in_dcache_in_address[3U] = vlTOPp->in_dcache_in_address
[3U];
vlSymsp->TOP__v.in_dcache_in_address[2U] = vlTOPp->in_dcache_in_address
[2U];
vlSymsp->TOP__v.in_dcache_in_address[1U] = vlTOPp->in_dcache_in_address
[1U];
vlSymsp->TOP__v.in_dcache_in_address[0U] = vlTOPp->in_dcache_in_address
[0U];
}
VL_INLINE_OPT void Vcache_simX::_combo__TOP__3(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_combo__TOP__3\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->out_icache_stall = ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__new_stored_valid)
| (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__state)));
}
VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_combo__TOP__5\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->out_dcache_stall = ((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))
| ((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_stored_valid))
| (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__state))));
}
void Vcache_simX::_eval(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_eval\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__1(vlSymsp);
vlTOPp->__Vm_traceActivity = (2U | vlTOPp->__Vm_traceActivity);
vlTOPp->_combo__TOP__1(vlSymsp);
if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))
| ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) {
vlSymsp->TOP__v__dmem_controller._sequent__TOP__v__dmem_controller__3(vlSymsp);
vlTOPp->__Vm_traceActivity = (4U | vlTOPp->__Vm_traceActivity);
vlSymsp->TOP__v._sequent__TOP__v__2(vlSymsp);
vlSymsp->TOP__v__dmem_controller._sequent__TOP__v__dmem_controller__4(vlSymsp);
}
vlSymsp->TOP__v._combo__TOP__v__3(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__5(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__7(vlSymsp);
if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))
| ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) {
vlSymsp->TOP__v__dmem_controller._sequent__TOP__v__dmem_controller__8(vlSymsp);
vlTOPp->__Vm_traceActivity = (8U | vlTOPp->__Vm_traceActivity);
}
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__10(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__12(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__14(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__16(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__18(vlSymsp);
vlTOPp->_combo__TOP__3(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__20(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__22(vlSymsp);
vlTOPp->_combo__TOP__5(vlSymsp);
// Final
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset;
}
void Vcache_simX::_eval_initial(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_eval_initial\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vcache_simX::final() {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::final\n"); );
// Variables
Vcache_simX__Syms* __restrict vlSymsp = this->__VlSymsp;
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vcache_simX::_eval_settle(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_eval_settle\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__1(vlSymsp);
vlTOPp->__Vm_traceActivity = (1U | vlTOPp->__Vm_traceActivity);
vlTOPp->_combo__TOP__1(vlSymsp);
vlSymsp->TOP__v._settle__TOP__v__1(vlSymsp);
vlSymsp->TOP__v._settle__TOP__v__4(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__6(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__9(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__11(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__13(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__15(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__17(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__19(vlSymsp);
vlTOPp->_combo__TOP__3(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__21(vlSymsp);
vlTOPp->_combo__TOP__5(vlSymsp);
}
VL_INLINE_OPT QData Vcache_simX::_change_request(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_change_request\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// Change detection
QData __req = false; // Logically a bool
__req |= ((vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_addr ^ vlTOPp->__Vchglast__TOP__v__dmem_controller__shared_memory__DOT__block_addr));
VL_DEBUG_IF( if(__req && ((vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_addr ^ vlTOPp->__Vchglast__TOP__v__dmem_controller__shared_memory__DOT__block_addr))) VL_PRINTF(" CHANGE: ../rtl/shared_memory/VX_shared_memory.v:49: shared_memory.block_addr\n"); );
// Final
vlTOPp->__Vchglast__TOP__v__dmem_controller__shared_memory__DOT__block_addr
= vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_addr;
return __req;
}

113
simX/obj_dir/Vcache_simX.h Normal file
View File

@@ -0,0 +1,113 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _Vcache_simX_H_
#define _Vcache_simX_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class Vcache_simX_cache_simX;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX) {
public:
// CELLS
// Public to allow access to /*verilator_public*/ items;
// otherwise the application code can consider these internals.
Vcache_simX_cache_simX* __PVT__v;
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(clk,0,0);
VL_IN8(reset,0,0);
VL_IN8(in_icache_valid_pc_addr,0,0);
VL_OUT8(out_icache_stall,0,0);
VL_IN8(in_dcache_mem_read,2,0);
VL_IN8(in_dcache_mem_write,2,0);
VL_OUT8(out_dcache_stall,0,0);
//char __VpadToAlign7[1];
VL_IN(in_icache_pc_addr,31,0);
VL_IN8(in_dcache_in_valid[4],0,0);
VL_IN(in_dcache_in_address[4],31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// LOCAL VARIABLES
// Internals; generally not touched by application code
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
//char __VpadToAlign42[2];
VL_SIG(__Vchglast__TOP__v__dmem_controller__shared_memory__DOT__block_addr,27,0);
VL_SIG(__Vm_traceActivity,31,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
Vcache_simX__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
Vcache_simX& operator= (const Vcache_simX&); ///< Copying not allowed
Vcache_simX(const Vcache_simX&); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible WRT DPI scope names.
Vcache_simX(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~Vcache_simX();
/// Trace signals in the model; called by application code
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp);
public:
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
static QData _change_request(Vcache_simX__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp);
static void _combo__TOP__3(Vcache_simX__Syms* __restrict vlSymsp);
static void _combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp);
static void _eval(Vcache_simX__Syms* __restrict vlSymsp);
static void _eval_initial(Vcache_simX__Syms* __restrict vlSymsp);
static void _eval_settle(Vcache_simX__Syms* __restrict vlSymsp);
static void traceChgThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__7(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__8(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__9(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceFullThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInitThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

91
simX/obj_dir/Vcache_simX.mk Normal file
View File

@@ -0,0 +1,91 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vcache_simX.mk
default: Vcache_simX
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/share/verilator
# Path to SystemPerl kit top (from $SYSTEMPERL)
SYSTEMPERL =
# Path to SystemPerl kit includes (from $SYSTEMPERL_INCLUDE)
SYSTEMPERL_INCLUDE =
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemPerl output mode? 0/1 (from --sp)
VM_SP = 0
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# SystemPerl or SystemC output mode? 0/1 (from --sp/--sc)
VM_SP_OR_SC = 0
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vcache_simX
# Module prefix (from --prefix)
VM_MODPREFIX = Vcache_simX
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-std=c++11 -fPIC -O3 \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
args \
core \
enc \
instruction \
mem \
simX \
util \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
. \
### Default rules...
# Include list of all generated classes
include Vcache_simX_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
args.o: args.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
core.o: core.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
enc.o: enc.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
instruction.o: instruction.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
mem.o: mem.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
simX.o: simX.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
util.o: util.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
Vcache_simX: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt
# Verilated -*- Makefile -*-

30
simX/obj_dir/Vcache_simX_VX_dcache_request_inter.cpp Normal file
View File

@@ -0,0 +1,30 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dcache_request_inter.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dcache_request_inter) {
// Reset internal values
// Reset structure values
VL_RAND_RESET_W(128,__PVT__out_cache_driver_in_address);
__PVT__out_cache_driver_in_valid = VL_RAND_RESET_I(4);
}
void Vcache_simX_VX_dcache_request_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dcache_request_inter::~Vcache_simX_VX_dcache_request_inter() {
}
//--------------------
// Internal Methods

55
simX/obj_dir/Vcache_simX_VX_dcache_request_inter.h Normal file
View File

@@ -0,0 +1,55 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dcache_request_inter_H_
#define _Vcache_simX_VX_dcache_request_inter_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dcache_request_inter) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
VL_SIG8(__PVT__out_cache_driver_in_valid,3,0);
//char __VpadToAlign5[3];
VL_SIGW(__PVT__out_cache_driver_in_address,127,0,4);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dcache_request_inter& operator= (const Vcache_simX_VX_dcache_request_inter&); ///< Copying not allowed
Vcache_simX_VX_dcache_request_inter(const Vcache_simX_VX_dcache_request_inter&); ///< Copying not allowed
public:
Vcache_simX_VX_dcache_request_inter(const char* name="TOP");
~Vcache_simX_VX_dcache_request_inter();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

28
simX/obj_dir/Vcache_simX_VX_dcache_response_inter.cpp Normal file
View File

@@ -0,0 +1,28 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dcache_response_inter.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dcache_response_inter) {
// Reset internal values
// Reset structure values
}
void Vcache_simX_VX_dcache_response_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dcache_response_inter::~Vcache_simX_VX_dcache_response_inter() {
}
//--------------------
// Internal Methods

53
simX/obj_dir/Vcache_simX_VX_dcache_response_inter.h Normal file
View File

@@ -0,0 +1,53 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dcache_response_inter_H_
#define _Vcache_simX_VX_dcache_response_inter_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dcache_response_inter) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
//char __VpadToAlign12[4];
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dcache_response_inter& operator= (const Vcache_simX_VX_dcache_response_inter&); ///< Copying not allowed
Vcache_simX_VX_dcache_response_inter(const Vcache_simX_VX_dcache_response_inter&); ///< Copying not allowed
public:
Vcache_simX_VX_dcache_response_inter(const char* name="TOP");
~Vcache_simX_VX_dcache_response_inter();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

13421
simX/obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.cpp Normal file
View File

File diff suppressed because it is too large Load Diff

1037
simX/obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.h Normal file
View File

File diff suppressed because it is too large Load Diff

29
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp Normal file
View File

@@ -0,0 +1,29 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
// Reset internal values
// Reset structure values
VL_RAND_RESET_W(128,__PVT__i_m_readdata);
}
void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4() {
}
//--------------------
// Internal Methods

54
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h Normal file
View File

@@ -0,0 +1,54 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
#define _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
//char __VpadToAlign4[4];
VL_SIGW(__PVT__i_m_readdata,127,0,4);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4& operator= (const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&); ///< Copying not allowed
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&); ///< Copying not allowed
public:
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const char* name="TOP");
~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

29
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp Normal file
View File

@@ -0,0 +1,29 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) {
// Reset internal values
// Reset structure values
VL_RAND_RESET_W(512,__PVT__i_m_readdata);
}
void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4() {
}
//--------------------
// Internal Methods

54
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h Normal file
View File

@@ -0,0 +1,54 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_
#define _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
//char __VpadToAlign4[4];
VL_SIGW(__PVT__i_m_readdata,511,0,16);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4& operator= (const Vcache_simX_VX_dram_req_rsp_inter__N4_NB4&); ///< Copying not allowed
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const Vcache_simX_VX_dram_req_rsp_inter__N4_NB4&); ///< Copying not allowed
public:
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const char* name="TOP");
~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

28
simX/obj_dir/Vcache_simX_VX_icache_request_inter.cpp Normal file
View File

@@ -0,0 +1,28 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_icache_request_inter.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_icache_request_inter) {
// Reset internal values
// Reset structure values
}
void Vcache_simX_VX_icache_request_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_icache_request_inter::~Vcache_simX_VX_icache_request_inter() {
}
//--------------------
// Internal Methods

53
simX/obj_dir/Vcache_simX_VX_icache_request_inter.h Normal file
View File

@@ -0,0 +1,53 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_icache_request_inter_H_
#define _Vcache_simX_VX_icache_request_inter_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_icache_request_inter) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
//char __VpadToAlign12[4];
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_icache_request_inter& operator= (const Vcache_simX_VX_icache_request_inter&); ///< Copying not allowed
Vcache_simX_VX_icache_request_inter(const Vcache_simX_VX_icache_request_inter&); ///< Copying not allowed
public:
Vcache_simX_VX_icache_request_inter(const char* name="TOP");
~Vcache_simX_VX_icache_request_inter();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

28
simX/obj_dir/Vcache_simX_VX_icache_response_inter.cpp Normal file
View File

@@ -0,0 +1,28 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_icache_response_inter.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_icache_response_inter) {
// Reset internal values
// Reset structure values
}
void Vcache_simX_VX_icache_response_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_icache_response_inter::~Vcache_simX_VX_icache_response_inter() {
}
//--------------------
// Internal Methods

53
simX/obj_dir/Vcache_simX_VX_icache_response_inter.h Normal file
View File

@@ -0,0 +1,53 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_icache_response_inter_H_
#define _Vcache_simX_VX_icache_response_inter_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_icache_response_inter) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
//char __VpadToAlign12[4];
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_icache_response_inter& operator= (const Vcache_simX_VX_icache_response_inter&); ///< Copying not allowed
Vcache_simX_VX_icache_response_inter(const Vcache_simX_VX_icache_response_inter&); ///< Copying not allowed
public:
Vcache_simX_VX_icache_response_inter(const char* name="TOP");
~Vcache_simX_VX_icache_response_inter();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

BIN
simX/obj_dir/Vcache_simX__ALL.a Normal file
View File

Binary file not shown.

11
simX/obj_dir/Vcache_simX__ALLcls.cpp Normal file
View File

@@ -0,0 +1,11 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vcache_simX.cpp"
#include "Vcache_simX_cache_simX.cpp"
#include "Vcache_simX_VX_dmem_controller__V0_VB1000.cpp"
#include "Vcache_simX_VX_icache_request_inter.cpp"
#include "Vcache_simX_VX_icache_response_inter.cpp"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
#include "Vcache_simX_VX_dcache_request_inter.cpp"
#include "Vcache_simX_VX_dcache_response_inter.cpp"

19
simX/obj_dir/Vcache_simX__ALLcls.d Normal file
View File

@@ -0,0 +1,19 @@
Vcache_simX__ALLcls.o: Vcache_simX__ALLcls.cpp Vcache_simX.cpp \
Vcache_simX.h /usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Inlines.h \
Vcache_simX__Syms.h Vcache_simX_cache_simX.h \
Vcache_simX_VX_dmem_controller__V0_VB1000.h \
Vcache_simX_VX_icache_request_inter.h \
Vcache_simX_VX_icache_response_inter.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
Vcache_simX_VX_dcache_request_inter.h \
Vcache_simX_VX_dcache_response_inter.h Vcache_simX_cache_simX.cpp \
Vcache_simX_VX_dmem_controller__V0_VB1000.cpp \
Vcache_simX_VX_icache_request_inter.cpp \
Vcache_simX_VX_icache_response_inter.cpp \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp \
Vcache_simX_VX_dcache_request_inter.cpp \
Vcache_simX_VX_dcache_response_inter.cpp

BIN
simX/obj_dir/Vcache_simX__ALLcls.o Normal file
View File

Binary file not shown.

5
simX/obj_dir/Vcache_simX__ALLsup.cpp Normal file
View File

@@ -0,0 +1,5 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vcache_simX__Trace.cpp"
#include "Vcache_simX__Syms.cpp"
#include "Vcache_simX__Trace__Slow.cpp"

14
simX/obj_dir/Vcache_simX__ALLsup.d Normal file
View File

@@ -0,0 +1,14 @@
Vcache_simX__ALLsup.o: Vcache_simX__ALLsup.cpp Vcache_simX__Trace.cpp \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Syms.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h Vcache_simX.h \
Vcache_simX__Inlines.h Vcache_simX_cache_simX.h \
Vcache_simX_VX_dmem_controller__V0_VB1000.h \
Vcache_simX_VX_icache_request_inter.h \
Vcache_simX_VX_icache_response_inter.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
Vcache_simX_VX_dcache_request_inter.h \
Vcache_simX_VX_dcache_response_inter.h Vcache_simX__Syms.cpp \
Vcache_simX__Trace__Slow.cpp

BIN
simX/obj_dir/Vcache_simX__ALLsup.o Normal file
View File

Binary file not shown.

23
simX/obj_dir/Vcache_simX__Inlines.h Normal file
View File

@@ -0,0 +1,23 @@
// Verilated -*- C++ -*-
#ifndef _Vcache_simX__Inlines_H_
#define _Vcache_simX__Inlines_H_
#include "verilated.h"
//======================
#ifndef VL_HAVE_CONST_W_16X
# define VL_HAVE_CONST_W_16X
static inline WDataOutP VL_CONST_W_16X(int obits, WDataOutP o
,IData d15,IData d14,IData d13,IData d12,IData d11,IData d10,IData d9,IData d8
,IData d7,IData d6,IData d5,IData d4,IData d3,IData d2,IData d1,IData d0) {
o[15]=d15; o[14]=d14; o[13]=d13; o[12]=d12; o[11]=d11; o[10]=d10; o[9]=d9; o[8]=d8;
o[7]=d7; o[6]=d6; o[5]=d5; o[4]=d4; o[3]=d3; o[2]=d2; o[1]=d1; o[0]=d0;
for(int i=16;i<VL_WORDS_I(obits);i++) o[i] = (IData)0x0;
return o;
}
#endif
//======================
#endif /*guard*/

53
simX/obj_dir/Vcache_simX__Syms.cpp Normal file
View File

@@ -0,0 +1,53 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vcache_simX__Syms.h"
#include "Vcache_simX.h"
#include "Vcache_simX_cache_simX.h"
#include "Vcache_simX_VX_dmem_controller__V0_VB1000.h"
#include "Vcache_simX_VX_icache_request_inter.h"
#include "Vcache_simX_VX_icache_response_inter.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_dcache_response_inter.h"
// FUNCTIONS
Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_activity(false)
, __Vm_didInit(false)
// Setup submodule names
, TOP__v (Verilated::catName(topp->name(),"v"))
, TOP__v__VX_dcache_req (Verilated::catName(topp->name(),"v.VX_dcache_req"))
, TOP__v__VX_dcache_rsp (Verilated::catName(topp->name(),"v.VX_dcache_rsp"))
, TOP__v__VX_dram_req_rsp (Verilated::catName(topp->name(),"v.VX_dram_req_rsp"))
, TOP__v__VX_dram_req_rsp_icache (Verilated::catName(topp->name(),"v.VX_dram_req_rsp_icache"))
, TOP__v__VX_icache_req (Verilated::catName(topp->name(),"v.VX_icache_req"))
, TOP__v__VX_icache_rsp (Verilated::catName(topp->name(),"v.VX_icache_rsp"))
, TOP__v__dmem_controller (Verilated::catName(topp->name(),"v.dmem_controller"))
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
TOPp->__PVT__v = &TOP__v;
TOPp->__PVT__v->__PVT__VX_dcache_req = &TOP__v__VX_dcache_req;
TOPp->__PVT__v->__PVT__VX_dcache_rsp = &TOP__v__VX_dcache_rsp;
TOPp->__PVT__v->__PVT__VX_dram_req_rsp = &TOP__v__VX_dram_req_rsp;
TOPp->__PVT__v->__PVT__VX_dram_req_rsp_icache = &TOP__v__VX_dram_req_rsp_icache;
TOPp->__PVT__v->__PVT__VX_icache_req = &TOP__v__VX_icache_req;
TOPp->__PVT__v->__PVT__VX_icache_rsp = &TOP__v__VX_icache_rsp;
TOPp->__PVT__v->__PVT__dmem_controller = &TOP__v__dmem_controller;
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
TOP__v.__Vconfigure(this, true);
TOP__v__VX_dcache_req.__Vconfigure(this, true);
TOP__v__VX_dcache_rsp.__Vconfigure(this, true);
TOP__v__VX_dram_req_rsp.__Vconfigure(this, true);
TOP__v__VX_dram_req_rsp_icache.__Vconfigure(this, true);
TOP__v__VX_icache_req.__Vconfigure(this, true);
TOP__v__VX_icache_rsp.__Vconfigure(this, true);
TOP__v__dmem_controller.__Vconfigure(this, true);
// Setup scope names
}

57
simX/obj_dir/Vcache_simX__Syms.h Normal file
View File

@@ -0,0 +1,57 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header
#ifndef _Vcache_simX__Syms_H_
#define _Vcache_simX__Syms_H_
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "Vcache_simX.h"
#include "Vcache_simX_cache_simX.h"
#include "Vcache_simX_VX_dmem_controller__V0_VB1000.h"
#include "Vcache_simX_VX_icache_request_inter.h"
#include "Vcache_simX_VX_icache_response_inter.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_dcache_response_inter.h"
// SYMS CLASS
class Vcache_simX__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_activity; ///< Used by trace routines to determine change occurred
bool __Vm_didInit;
//char __VpadToAlign10[6];
// SUBCELL STATE
Vcache_simX* TOPp;
Vcache_simX_cache_simX TOP__v;
Vcache_simX_VX_dcache_request_inter TOP__v__VX_dcache_req;
Vcache_simX_VX_dcache_response_inter TOP__v__VX_dcache_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__v__VX_dram_req_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 TOP__v__VX_dram_req_rsp_icache;
Vcache_simX_VX_icache_request_inter TOP__v__VX_icache_req;
Vcache_simX_VX_icache_response_inter TOP__v__VX_icache_rsp;
Vcache_simX_VX_dmem_controller__V0_VB1000 TOP__v__dmem_controller;
// COVERAGE
// SCOPE NAMES
// CREATORS
Vcache_simX__Syms(Vcache_simX* topp, const char* namep);
~Vcache_simX__Syms() {};
// METHODS
inline const char* name() { return __Vm_namep; }
inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r;}
} VL_ATTR_ALIGNED(64);
#endif /*guard*/

5777
simX/obj_dir/Vcache_simX__Trace.cpp Normal file
View File

File diff suppressed because it is too large Load Diff

7599
simX/obj_dir/Vcache_simX__Trace__Slow.cpp Normal file
View File

File diff suppressed because it is too large Load Diff

1
simX/obj_dir/Vcache_simX__ver.d Normal file
View File

@@ -0,0 +1 @@
obj_dir/Vcache_simX.cpp obj_dir/Vcache_simX.h obj_dir/Vcache_simX.mk obj_dir/Vcache_simX_VX_dcache_request_inter.cpp obj_dir/Vcache_simX_VX_dcache_request_inter.h obj_dir/Vcache_simX_VX_dcache_response_inter.cpp obj_dir/Vcache_simX_VX_dcache_response_inter.h obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.cpp obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h obj_dir/Vcache_simX_VX_icache_request_inter.cpp obj_dir/Vcache_simX_VX_icache_request_inter.h obj_dir/Vcache_simX_VX_icache_response_inter.cpp obj_dir/Vcache_simX_VX_icache_response_inter.h obj_dir/Vcache_simX__Inlines.h obj_dir/Vcache_simX__Syms.cpp obj_dir/Vcache_simX__Syms.h obj_dir/Vcache_simX__Trace.cpp obj_dir/Vcache_simX__Trace__Slow.cpp obj_dir/Vcache_simX__ver.d obj_dir/Vcache_simX_cache_simX.cpp obj_dir/Vcache_simX_cache_simX.h obj_dir/Vcache_simX_classes.mk : /usr/bin/verilator_bin ../rtl/./VX_define_synth.v ../rtl/VX_countones.v ../rtl/VX_define.v ../rtl/VX_dmem_controller.v ../rtl/VX_generic_priority_encoder.v ../rtl/VX_priority_encoder_w_mask.v ../rtl/cache/VX_Cache_Bank.v ../rtl/cache/VX_cache_bank_valid.v ../rtl/cache/VX_cache_data.v ../rtl/cache/VX_cache_data_per_index.v ../rtl/cache/VX_d_cache.v ../rtl/interfaces/VX_dcache_request_inter.v ../rtl/interfaces/VX_dcache_response_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_icache_request_inter.v ../rtl/interfaces/VX_icache_response_inter.v ../rtl/shared_memory/../VX_define.v ../rtl/shared_memory/VX_bank_valids.v ../rtl/shared_memory/VX_priority_encoder_sm.v ../rtl/shared_memory/VX_shared_memory.v ../rtl/shared_memory/VX_shared_memory_block.v /usr/bin/verilator_bin cache_simX.v

52
simX/obj_dir/Vcache_simX__verFiles.dat Normal file
View File

@@ -0,0 +1,52 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
S 26 40239138 1574470136 "../rtl/./VX_define_synth.v"
S 283 40239133 1574470136 "../rtl/VX_countones.v"
S 7240 40239137 1574470136 "../rtl/VX_define.v"
S 8325 40239139 1574470136 "../rtl/VX_dmem_controller.v"
S 517 40239143 1574470136 "../rtl/VX_generic_priority_encoder.v"
S 683 40239154 1574470136 "../rtl/VX_priority_encoder_w_mask.v"
S 8590 40239164 1574470136 "../rtl/cache/VX_Cache_Bank.v"
S 748 40239165 1574470136 "../rtl/cache/VX_cache_bank_valid.v"
S 7349 40239166 1574470136 "../rtl/cache/VX_cache_data.v"
S 6476 40239167 1574470136 "../rtl/cache/VX_cache_data_per_index.v"
S 14645 40239168 1574470136 "../rtl/cache/VX_d_cache.v"
S 393 40239180 1574470136 "../rtl/interfaces/VX_dcache_request_inter.v"
S 215 40239181 1574470136 "../rtl/interfaces/VX_dcache_response_inter.v"
S 870 40239182 1574470136 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
S 354 40239191 1574470136 "../rtl/interfaces/VX_icache_request_inter.v"
S 212 40239192 1574470136 "../rtl/interfaces/VX_icache_response_inter.v"
S 7240 40239137 1574470136 "../rtl/shared_memory/../VX_define.v"
S 676 40239236 1574470136 "../rtl/shared_memory/VX_bank_valids.v"
S 3038 40239237 1574470136 "../rtl/shared_memory/VX_priority_encoder_sm.v"
S 4962 40239238 1574470136 "../rtl/shared_memory/VX_shared_memory.v"
S 3207 40239239 1574470136 "../rtl/shared_memory/VX_shared_memory_block.v"
S 4117944 1442940 1433741508 "/usr/bin/verilator_bin"
S 3144 40239440 1574470137 "cache_simX.v"
T 9461 40501257 1574470340 "obj_dir/Vcache_simX.cpp"
T 5060 40501256 1574470340 "obj_dir/Vcache_simX.h"
T 2505 40501275 1574470341 "obj_dir/Vcache_simX.mk"
T 836 40501271 1574470341 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
T 1627 40501270 1574470341 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
T 721 40501273 1574470341 "obj_dir/Vcache_simX_VX_dcache_response_inter.cpp"
T 1529 40501272 1574470341 "obj_dir/Vcache_simX_VX_dcache_response_inter.h"
T 1690042 40501261 1574470341 "obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.cpp"
T 145427 40501260 1574470340 "obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.h"
T 792 40501269 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
T 1615 40501268 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
T 792 40501267 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
T 1616 40501266 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
T 716 40501263 1574470341 "obj_dir/Vcache_simX_VX_icache_request_inter.cpp"
T 1520 40501262 1574470341 "obj_dir/Vcache_simX_VX_icache_request_inter.h"
T 721 40501265 1574470341 "obj_dir/Vcache_simX_VX_icache_response_inter.cpp"
T 1529 40501264 1574470341 "obj_dir/Vcache_simX_VX_icache_response_inter.h"
T 735 40501251 1574470340 "obj_dir/Vcache_simX__Inlines.h"
T 2656 40501253 1574470340 "obj_dir/Vcache_simX__Syms.cpp"
T 1907 40501252 1574470340 "obj_dir/Vcache_simX__Syms.h"
T 656053 40501255 1574470340 "obj_dir/Vcache_simX__Trace.cpp"
T 854791 40501254 1574470340 "obj_dir/Vcache_simX__Trace__Slow.cpp"
T 1868 40501276 1574470341 "obj_dir/Vcache_simX__ver.d"
T 0 0 1574470341 "obj_dir/Vcache_simX__verFiles.dat"
T 5999 40501259 1574470340 "obj_dir/Vcache_simX_cache_simX.cpp"
T 2955 40501258 1574470340 "obj_dir/Vcache_simX_cache_simX.h"
T 1488 40501274 1574470341 "obj_dir/Vcache_simX_classes.mk"

131
simX/obj_dir/Vcache_simX_cache_simX.cpp Normal file
View File

@@ -0,0 +1,131 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_cache_simX.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_cache_simX) {
VL_CELL (__PVT__VX_icache_req, Vcache_simX_VX_icache_request_inter);
VL_CELL (__PVT__VX_icache_rsp, Vcache_simX_VX_icache_response_inter);
VL_CELL (__PVT__VX_dram_req_rsp_icache, Vcache_simX_VX_dram_req_rsp_inter__N1_NB4);
VL_CELL (__PVT__VX_dcache_req, Vcache_simX_VX_dcache_request_inter);
VL_CELL (__PVT__VX_dcache_rsp, Vcache_simX_VX_dcache_response_inter);
VL_CELL (__PVT__VX_dram_req_rsp, Vcache_simX_VX_dram_req_rsp_inter__N4_NB4);
VL_CELL (__PVT__dmem_controller, Vcache_simX_VX_dmem_controller__V0_VB1000);
// Reset internal values
// Reset structure values
clk = VL_RAND_RESET_I(1);
reset = VL_RAND_RESET_I(1);
in_icache_pc_addr = VL_RAND_RESET_I(32);
in_icache_valid_pc_addr = VL_RAND_RESET_I(1);
out_icache_stall = VL_RAND_RESET_I(1);
in_dcache_mem_read = VL_RAND_RESET_I(3);
in_dcache_mem_write = VL_RAND_RESET_I(3);
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
in_dcache_in_valid[__Vi0] = VL_RAND_RESET_I(1);
}}
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
in_dcache_in_address[__Vi0] = VL_RAND_RESET_I(32);
}}
out_dcache_stall = VL_RAND_RESET_I(1);
__PVT__icache_i_m_ready = VL_RAND_RESET_I(1);
__PVT__dcache_i_m_ready = VL_RAND_RESET_I(1);
}
void Vcache_simX_cache_simX::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_cache_simX::~Vcache_simX_cache_simX() {
}
//--------------------
// Internal Methods
void Vcache_simX_cache_simX::_settle__TOP__v__1(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX_cache_simX::_settle__TOP__v__1\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xeU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| vlSymsp->TOP__v.in_dcache_in_valid[0U]);
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xdU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[1U]
<< 1U));
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xbU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[2U]
<< 2U));
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((7U & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[3U]
<< 3U));
}
VL_INLINE_OPT void Vcache_simX_cache_simX::_sequent__TOP__v__2(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX_cache_simX::_sequent__TOP__v__2\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// ALWAYS at cache_simX.v:93
if (vlTOPp->reset) {
vlSymsp->TOP__v.__PVT__icache_i_m_ready = 0U;
vlSymsp->TOP__v.__PVT__dcache_i_m_ready = 0U;
} else {
vlSymsp->TOP__v.__PVT__icache_i_m_ready = (1U
== (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__state));
vlSymsp->TOP__v.__PVT__dcache_i_m_ready = (1U
== (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__state));
}
}
VL_INLINE_OPT void Vcache_simX_cache_simX::_combo__TOP__v__3(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX_cache_simX::_combo__TOP__v__3\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xeU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| vlSymsp->TOP__v.in_dcache_in_valid[0U]);
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xdU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[1U]
<< 1U));
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xbU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[2U]
<< 2U));
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((7U & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[3U]
<< 3U));
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[0U]
= vlSymsp->TOP__v.in_dcache_in_address[0U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[1U]
= vlSymsp->TOP__v.in_dcache_in_address[1U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[2U]
= vlSymsp->TOP__v.in_dcache_in_address[2U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[3U]
= vlSymsp->TOP__v.in_dcache_in_address[3U];
}
void Vcache_simX_cache_simX::_settle__TOP__v__4(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX_cache_simX::_settle__TOP__v__4\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[0U]
= vlSymsp->TOP__v.in_dcache_in_address[0U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[1U]
= vlSymsp->TOP__v.in_dcache_in_address[1U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[2U]
= vlSymsp->TOP__v.in_dcache_in_address[2U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[3U]
= vlSymsp->TOP__v.in_dcache_in_address[3U];
}

84
simX/obj_dir/Vcache_simX_cache_simX.h Normal file
View File

@@ -0,0 +1,84 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_cache_simX_H_
#define _Vcache_simX_cache_simX_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class Vcache_simX_VX_icache_request_inter;
class Vcache_simX_VX_icache_response_inter;
class Vcache_simX_VX_dram_req_rsp_inter__N1_NB4;
class Vcache_simX_VX_dcache_request_inter;
class Vcache_simX_VX_dcache_response_inter;
class Vcache_simX_VX_dram_req_rsp_inter__N4_NB4;
class Vcache_simX_VX_dmem_controller__V0_VB1000;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_cache_simX) {
public:
// CELLS
Vcache_simX_VX_icache_request_inter* __PVT__VX_icache_req;
Vcache_simX_VX_icache_response_inter* __PVT__VX_icache_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4* __PVT__VX_dram_req_rsp_icache;
Vcache_simX_VX_dcache_request_inter* __PVT__VX_dcache_req;
Vcache_simX_VX_dcache_response_inter* __PVT__VX_dcache_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4* __PVT__VX_dram_req_rsp;
Vcache_simX_VX_dmem_controller__V0_VB1000* __PVT__dmem_controller;
// PORTS
VL_IN8(clk,0,0);
VL_IN8(reset,0,0);
VL_IN8(in_icache_valid_pc_addr,0,0);
VL_OUT8(out_icache_stall,0,0);
VL_IN8(in_dcache_mem_read,2,0);
VL_IN8(in_dcache_mem_write,2,0);
VL_OUT8(out_dcache_stall,0,0);
//char __VpadToAlign7[1];
VL_IN(in_icache_pc_addr,31,0);
VL_IN8(in_dcache_in_valid[4],0,0);
VL_IN(in_dcache_in_address[4],31,0);
// LOCAL SIGNALS
VL_SIG8(__PVT__icache_i_m_ready,0,0);
VL_SIG8(__PVT__dcache_i_m_ready,0,0);
//char __VpadToAlign38[2];
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_cache_simX& operator= (const Vcache_simX_cache_simX&); ///< Copying not allowed
Vcache_simX_cache_simX(const Vcache_simX_cache_simX&); ///< Copying not allowed
public:
Vcache_simX_cache_simX(const char* name="TOP");
~Vcache_simX_cache_simX();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void _combo__TOP__v__3(Vcache_simX__Syms* __restrict vlSymsp);
static void _sequent__TOP__v__2(Vcache_simX__Syms* __restrict vlSymsp);
static void _settle__TOP__v__1(Vcache_simX__Syms* __restrict vlSymsp);
static void _settle__TOP__v__4(Vcache_simX__Syms* __restrict vlSymsp);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

47
simX/obj_dir/Vcache_simX_classes.mk Normal file
View File

@@ -0,0 +1,47 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vcache_simX.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 1
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vcache_simX \
Vcache_simX_cache_simX \
Vcache_simX_VX_dmem_controller__V0_VB1000 \
Vcache_simX_VX_icache_request_inter \
Vcache_simX_VX_icache_response_inter \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 \
Vcache_simX_VX_dcache_request_inter \
Vcache_simX_VX_dcache_response_inter \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
Vcache_simX__Trace \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vcache_simX__Syms \
Vcache_simX__Trace__Slow \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
verilated_vcd_c \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

1
simX/obj_dir/args.d Normal file
View File

@@ -0,0 +1 @@
args.o: ../args.cpp ../include/args.h

BIN
simX/obj_dir/args.o Normal file
View File

Binary file not shown.

10
simX/obj_dir/core.d Normal file
View File

@@ -0,0 +1,10 @@
core.o: ../core.cpp ../include/types.h ../include/util.h \
../include/types.h ../include/archdef.h ../include/mem.h \
../include/enc.h ../include/instruction.h ../include/trace.h \
../include/obj.h ../include/archdef.h ../include/enc.h \
../include/asm-tokens.h ../include/core.h ../include/mem.h \
../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Inlines.h \
/usr/share/verilator/include/verilated_vcd_c.h ../include/debug.h

BIN
simX/obj_dir/core.o Normal file
View File

Binary file not shown.

2342055
simX/obj_dir/emulator.debug Normal file
View File

File diff suppressed because it is too large Load Diff

5
simX/obj_dir/enc.d Normal file
View File

@@ -0,0 +1,5 @@
enc.o: ../enc.cpp ../include/debug.h ../include/types.h ../include/util.h \
../include/types.h ../include/enc.h ../include/instruction.h \
../include/trace.h ../include/obj.h ../include/archdef.h \
../include/enc.h ../include/asm-tokens.h ../include/archdef.h \
../include/instruction.h

BIN
simX/obj_dir/enc.o Normal file
View File

Binary file not shown.

10
simX/obj_dir/instruction.d Normal file
View File

@@ -0,0 +1,10 @@
instruction.o: ../instruction.cpp ../include/instruction.h \
../include/types.h ../include/trace.h ../include/obj.h \
../include/archdef.h ../include/instruction.h ../include/enc.h \
../include/obj.h ../include/asm-tokens.h ../include/core.h \
../include/mem.h ../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Inlines.h \
/usr/share/verilator/include/verilated_vcd_c.h ../include/harpfloat.h \
../include/debug.h

BIN
simX/obj_dir/instruction.o Normal file
View File

Binary file not shown.

9
simX/obj_dir/mem.d Normal file
View File

@@ -0,0 +1,9 @@
mem.o: ../mem.cpp ../include/debug.h ../include/types.h ../include/util.h \
../include/types.h ../include/mem.h ../include/core.h \
../include/archdef.h ../include/enc.h ../include/instruction.h \
../include/trace.h ../include/obj.h ../include/asm-tokens.h \
../include/mem.h ../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Inlines.h \
/usr/share/verilator/include/verilated_vcd_c.h

BIN
simX/obj_dir/mem.o Normal file
View File

Binary file not shown.

11
simX/obj_dir/simX.d Normal file
View File

@@ -0,0 +1,11 @@
simX.o: ../simX.cpp ../include/debug.h ../include/types.h \
../include/core.h ../include/types.h ../include/archdef.h \
../include/enc.h ../include/instruction.h ../include/trace.h \
../include/obj.h ../include/asm-tokens.h ../include/mem.h \
../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Inlines.h \
/usr/share/verilator/include/verilated_vcd_c.h ../include/enc.h \
../include/instruction.h ../include/mem.h ../include/obj.h \
../include/archdef.h ../include/args.h ../include/help.h

BIN
simX/obj_dir/simX.o Normal file
View File

Binary file not shown.

2
simX/obj_dir/util.d Normal file
View File

@@ -0,0 +1,2 @@
util.o: ../util.cpp ../include/types.h ../include/util.h \
../include/types.h

BIN
simX/obj_dir/util.o Normal file
View File

Binary file not shown.

7
simX/obj_dir/verilated.d Normal file
View File

@@ -0,0 +1,7 @@
verilated.o: /usr/share/verilator/include/verilated.cpp \
/usr/share/verilator/include/verilated_imp.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_heavy.h \
/usr/share/verilator/include/verilated_syms.h

BIN
simX/obj_dir/verilated.o Normal file
View File

Binary file not shown.

5
simX/obj_dir/verilated_vcd_c.d Normal file
View File

@@ -0,0 +1,5 @@
verilated_vcd_c.o: /usr/share/verilator/include/verilated_vcd_c.cpp \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_vcd_c.h

BIN
simX/obj_dir/verilated_vcd_c.o Normal file
View File

Binary file not shown.

2
simX/test_riscv.sh
View File

@@ -3,4 +3,4 @@ echo start > results.txt
# echo ../kernel/vortex_test.hex
make
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../runtime/mains/vector_test/vx_vector_main.hex -s -b 1> emulator.debug
cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug

6
simX/test_vec.sh Executable file
View File

@@ -0,0 +1,6 @@
echo start > results.txt
# echo ../kernel/vortex_test.hex
make
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../rvvector/basic/vx_vector_main.hex -s -b 1> emulator.debug

2
simX/util.cpp
View File

@@ -52,7 +52,7 @@ Byte Harp::readByte(const vector<Byte> &b, Size &n) {
}
Word_u Harp::readWord(const vector<Byte> &b, Size &n, Size wordSize) {
if (b.size() - n < wordSize) throw OutOfBytes();
// if (b.size() - n < wordSize) throw OutOfBytes();
Word_u w(0);
n += wordSize;
// std::cout << "wordSize: " << wordSize << "\n";