wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

merge

Browse Source
This commit is contained in:
Blaise Tine
2020-06-03 06:25:34 -04:00
parent 106d707024 04fc34b848
commit 626a4f6fc1
27 changed files with 383 additions and 314 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
driver/opae/vortex.cpp
View File

@@ -246,8 +246,12 @@ extern int vx_ready_wait(vx_device_h hdevice, long long timeout) {
for (;;) { for (;;) {
CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_STATUS, &data)); CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_STATUS, &data));
if (0 == data || 0 == timeout) if (0 == data || 0 == timeout) {
if (data != 0) {
fprintf(stdout, "ready-wait timed out: status=%ld\n", data);
}
break; break;
}
nanosleep(&sleep_time, nullptr); nanosleep(&sleep_time, nullptr);
timeout -= sleep_time_ms; timeout -= sleep_time_ms;
}; };

1
driver/rtlsim/Makefile
View File

@@ -37,6 +37,7 @@ RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../
VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(MULTICORE) VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(MULTICORE)
VL_FLAGS += -Wno-DECLFILENAME VL_FLAGS += -Wno-DECLFILENAME
VL_FLAGS += --x-initial unique VL_FLAGS += --x-initial unique
VL_FLAGS += --x-assign unique
# Enable Verilator multithreaded simulation # Enable Verilator multithreaded simulation
#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')

0
driver/tests/basic/kernel.bin Executable file → Normal file
View File

28
driver/tests/demo/demo.cpp
View File

@@ -91,7 +91,7 @@ int run_test(vx_device_h device,
int ref = i + i; int ref = i + i;
int cur = buf_ptr[i]; int cur = buf_ptr[i];
if (cur != ref) { if (cur != ref) {
std::cout << "error at 0x" << std::hex << (buf_ptr + i) std::cout << "error at value " << i
<< ": actual 0x" << cur << ", expected 0x" << ref << std::endl; << ": actual 0x" << cur << ", expected 0x" << ref << std::endl;
++errors; ++errors;
} }
@@ -150,23 +150,39 @@ int main(int argc, char *argv[]) {
RT_CHECK(vx_alloc_dev_mem(device, buf_size, &value)); RT_CHECK(vx_alloc_dev_mem(device, buf_size, &value));
kernel_arg.dst_ptr = value; kernel_arg.dst_ptr = value;
std::cout << "dev_src0=" << std::hex << kernel_arg.src0_ptr << std::endl;
std::cout << "dev_src1=" << std::hex << kernel_arg.src1_ptr << std::endl;
std::cout << "dev_dst=" << std::hex << kernel_arg.dst_ptr << std::endl;
// allocate shared memory // allocate shared memory
std::cout << "allocate shared memory" << std::endl; std::cout << "allocate shared memory" << std::endl;
uint32_t alloc_size = std::max<uint32_t>(buf_size, sizeof(kernel_arg_t)); uint32_t alloc_size = std::max<uint32_t>(buf_size, sizeof(kernel_arg_t));
RT_CHECK(vx_alloc_shared_mem(device, alloc_size, &buffer)); RT_CHECK(vx_alloc_shared_mem(device, alloc_size, &buffer));
// populate source buffer values // populate source buffer0 values
std::cout << "populate source buffer values" << std::endl; std::cout << "populate source buffer0 values" << std::endl;
{ {
auto buf_ptr = (int*)vx_host_ptr(buffer); auto buf_ptr = (int*)vx_host_ptr(buffer);
for (uint32_t i = 0; i < num_points; ++i) { for (uint32_t i = 0; i < num_points; ++i) {
buf_ptr[i] = i; buf_ptr[i] = i-1;
} }
} }
// upload source buffers // upload source buffer0
std::cout << "upload source buffers" << std::endl; std::cout << "upload source buffer0" << std::endl;
RT_CHECK(vx_copy_to_dev(buffer, kernel_arg.src0_ptr, buf_size, 0)); RT_CHECK(vx_copy_to_dev(buffer, kernel_arg.src0_ptr, buf_size, 0));
// populate source buffer1 values
std::cout << "populate source buffer1 values" << std::endl;
{
auto buf_ptr = (int*)vx_host_ptr(buffer);
for (uint32_t i = 0; i < num_points; ++i) {
buf_ptr[i] = i+1;
}
}
// upload source buffer1
std::cout << "upload source buffer1" << std::endl;
RT_CHECK(vx_copy_to_dev(buffer, kernel_arg.src1_ptr, buf_size, 0)); RT_CHECK(vx_copy_to_dev(buffer, kernel_arg.src1_ptr, buf_size, 0));
// upload kernel argument // upload kernel argument

2
hw/opae/README
View File

@@ -82,4 +82,4 @@ ps -u tinebp
kill -9 <pid> kill -9 <pid>
# fixing device resource busy issue when deleting /build_ase/ # fixing device resource busy issue when deleting /build_ase/
lsof +D build_ase -

15
hw/opae/sources.txt
View File

@@ -7,6 +7,7 @@ vortex_afu.json
+define+NUM_CORES=2 +define+NUM_CORES=2
+define+NUM_WARPS=4 +define+NUM_WARPS=4
+define+NUM_THREADS=4 +define+NUM_THREADS=4
+define+L2_ENABLE=1
+define+DNUM_BANKS=4 +define+DNUM_BANKS=4
+define+INUM_BANKS=1 +define+INUM_BANKS=1
@@ -16,13 +17,13 @@ vortex_afu.json
+define+IDFPQ_SIZE=16 +define+IDFPQ_SIZE=16
+define+SDFPQ_SIZE=0 +define+SDFPQ_SIZE=0
+define+DBG_PRINT_CORE_ICACHE #+define+DBG_PRINT_CORE_ICACHE
+define+DBG_PRINT_CORE_DCACHE #+define+DBG_PRINT_CORE_DCACHE
+define+DBG_PRINT_CACHE_BANK #+define+DBG_PRINT_CACHE_BANK
+define+DBG_PRINT_CACHE_SNP #+define+DBG_PRINT_CACHE_SNP
+define+DBG_PRINT_CACHE_MSRQ #+define+DBG_PRINT_CACHE_MSRQ
+define+DBG_PRINT_DRAM #+define+DBG_PRINT_DRAM
+define+DBG_PRINT_OPAE #+define+DBG_PRINT_OPAE
+incdir+. +incdir+.
+incdir+../rtl +incdir+../rtl

214
hw/opae/vortex_afu.sv
View File

@@ -1,6 +1,16 @@
`ifndef NOPAE
`include "platform_if.vh" `include "platform_if.vh"
import local_mem_cfg_pkg::*; import local_mem_cfg_pkg::*;
`include "afu_json_info.vh" `include "afu_json_info.vh"
`include "VX_define.vh"
`else
`include "vortex_afu.vh"
/* verilator lint_off IMPORTSTAR */
import ccip_if_pkg::*;
import local_mem_cfg_pkg::*;
/* verilator lint_on IMPORTSTAR */
`endif
`include "VX_define.vh" `include "VX_define.vh"
`define VX_TO_DRAM_ADDR(x) x[`VX_DRAM_ADDR_WIDTH-1:(`VX_DRAM_ADDR_WIDTH-DRAM_ADDR_WIDTH)] `define VX_TO_DRAM_ADDR(x) x[`VX_DRAM_ADDR_WIDTH-1:(`VX_DRAM_ADDR_WIDTH-DRAM_ADDR_WIDTH)]
@@ -93,55 +103,68 @@ logic [`VX_SNP_TAG_WIDTH-1:0] vx_snp_req_tag;
logic vx_snp_req_ready; logic vx_snp_req_ready;
logic vx_snp_rsp_valid; logic vx_snp_rsp_valid;
`DEBUG_BEGIN
logic [`VX_SNP_TAG_WIDTH-1:0] vx_snp_rsp_tag; logic [`VX_SNP_TAG_WIDTH-1:0] vx_snp_rsp_tag;
`DEBUG_END
logic vx_snp_rsp_ready; logic vx_snp_rsp_ready;
logic vx_reset;
logic vx_busy; logic vx_busy;
// AVS Queues ///////////////////////////////////////////////////////////////// // AVS Queues /////////////////////////////////////////////////////////////////
logic avs_rtq_push; logic avs_rtq_push;
logic avs_rtq_pop; logic avs_rtq_pop;
`DEBUG_BEGIN
logic avs_rtq_empty; logic avs_rtq_empty;
logic avs_rtq_full; logic avs_rtq_full;
`DEBUG_BEGIN
logic avs_rdq_push; logic avs_rdq_push;
logic avs_rdq_pop; logic avs_rdq_pop;
t_local_mem_data avs_rdq_dout; t_local_mem_data avs_rdq_dout;
logic avs_rdq_empty; logic avs_rdq_empty;
`DEBUG_BEGIN
logic avs_rdq_full; logic avs_rdq_full;
`DEBUG_END
// CSR variables ////////////////////////////////////////////////////////////// // CSR variables //////////////////////////////////////////////////////////////
logic [2:0] csr_cmd; logic [2:0] csr_cmd;
t_ccip_clAddr csr_io_addr; t_ccip_clAddr csr_io_addr;
t_local_mem_addr csr_mem_addr; logic[DRAM_ADDR_WIDTH-1:0] csr_mem_addr;
t_ccip_clAddr csr_data_size; logic[DRAM_ADDR_WIDTH-1:0] csr_data_size;
// MMIO controller //////////////////////////////////////////////////////////// // MMIO controller ////////////////////////////////////////////////////////////
t_ccip_c0_ReqMmioHdr mmioHdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr); `IGNORE_WARNINGS_BEGIN
t_ccip_c0_ReqMmioHdr mmio_hdr;
`IGNORE_WARNINGS_END
assign mmio_hdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr);
t_if_ccip_c2_Tx mmio_tx;
assign af2cp_sTxPort.c2 = mmio_tx;
always_ff @(posedge clk) always_ff @(posedge clk)
begin begin
if (SoftReset) begin if (SoftReset) begin
af2cp_sTxPort.c2.hdr <= 0; mmio_tx.hdr <= 0;
af2cp_sTxPort.c2.data <= 0; mmio_tx.data <= 0;
af2cp_sTxPort.c2.mmioRdValid <= 0; mmio_tx.mmioRdValid <= 0;
csr_cmd <= 0; csr_cmd <= 0;
csr_io_addr <= 0; csr_io_addr <= 0;
csr_mem_addr <= 0; csr_mem_addr <= 0;
csr_data_size <= 0; csr_data_size <= 0;
end end
else begin else begin
csr_cmd <= 0; csr_cmd <= 0;
af2cp_sTxPort.c2.mmioRdValid <= 0; mmio_tx.mmioRdValid <= 0;
// serve MMIO write request // serve MMIO write request
if (cp2af_sRxPort.c0.mmioWrValid) if (cp2af_sRxPort.c0.mmioWrValid)
begin begin
case (mmioHdr.address) case (mmio_hdr.address)
MMIO_CSR_IO_ADDR: begin MMIO_CSR_IO_ADDR: begin
csr_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data); csr_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data);
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
@@ -168,7 +191,7 @@ begin
end end
default: begin default: begin
// user-defined CSRs // user-defined CSRs
//if (mmioHdr.addres >= MMIO_CSR_USER) begin //if (mmio_hdr.addres >= MMIO_CSR_USER) begin
// write Vortex CRS // write Vortex CRS
//end //end
end end
@@ -177,10 +200,10 @@ begin
// serve MMIO read requests // serve MMIO read requests
if (cp2af_sRxPort.c0.mmioRdValid) begin if (cp2af_sRxPort.c0.mmioRdValid) begin
af2cp_sTxPort.c2.hdr.tid <= mmioHdr.tid; // copy TID mmio_tx.hdr.tid <= mmio_hdr.tid; // copy TID
case (mmioHdr.address) case (mmio_hdr.address)
// AFU header // AFU header
16'h0000: af2cp_sTxPort.c2.data <= { 16'h0000: mmio_tx.data <= {
4'b0001, // Feature type = AFU 4'b0001, // Feature type = AFU
8'b0, // reserved 8'b0, // reserved
4'b0, // afu minor revision = 0 4'b0, // afu minor revision = 0
@@ -190,37 +213,31 @@ begin
4'b0, // afu major revision = 0 4'b0, // afu major revision = 0
12'b0 // feature ID = 0 12'b0 // feature ID = 0
}; };
AFU_ID_L: af2cp_sTxPort.c2.data <= afu_id[63:0]; // afu id low AFU_ID_L: mmio_tx.data <= afu_id[63:0]; // afu id low
AFU_ID_H: af2cp_sTxPort.c2.data <= afu_id[127:64]; // afu id hi AFU_ID_H: mmio_tx.data <= afu_id[127:64]; // afu id hi
16'h0006: af2cp_sTxPort.c2.data <= 64'h0; // next AFU 16'h0006: mmio_tx.data <= 64'h0; // next AFU
16'h0008: af2cp_sTxPort.c2.data <= 64'h0; // reserved 16'h0008: mmio_tx.data <= 64'h0; // reserved
MMIO_CSR_STATUS: begin MMIO_CSR_STATUS: begin
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
if (state != af2cp_sTxPort.c2.data) begin if (state != mmio_tx.data) begin
$display("%t: STATUS: state=%0d", $time, state); $display("%t: STATUS: state=%0d", $time, state);
end end
`endif `endif
af2cp_sTxPort.c2.data <= state; mmio_tx.data <= {60'b0, state};
end end
default: af2cp_sTxPort.c2.data <= 64'h0; default: mmio_tx.data <= 64'h0;
endcase endcase
af2cp_sTxPort.c2.mmioRdValid <= 1; // post response mmio_tx.mmioRdValid <= 1; // post response
end end
end end
end end
// COMMAND FSM //////////////////////////////////////////////////////////////// // COMMAND FSM ////////////////////////////////////////////////////////////////
t_ccip_clAddr cci_wr_req_ctr;
logic [DRAM_ADDR_WIDTH-1:0] avs_rd_req_ctr;
logic [DRAM_ADDR_WIDTH-1:0] avs_wr_req_ctr;
logic vx_reset;
logic cmd_read_done; logic cmd_read_done;
logic cmd_write_done; logic cmd_write_done;
logic cmd_clflush_done; logic cmd_clflush_done;
logic cmd_run_done;
logic cmd_run_done = !vx_busy;
always_ff @(posedge clk) always_ff @(posedge clk)
begin begin
@@ -260,6 +277,9 @@ begin
`endif `endif
state <= STATE_CLFLUSH; state <= STATE_CLFLUSH;
end end
default: begin
state <= state;
end
endcase endcase
end end
@@ -291,6 +311,10 @@ begin
end end
end end
default: begin
state <= state;
end
endcase endcase
end end
end end
@@ -304,7 +328,9 @@ t_cci_rdq_data cci_rdq_dout;
logic cci_dram_rd_req_fire; logic cci_dram_rd_req_fire;
logic cci_dram_wr_req_fire; logic cci_dram_wr_req_fire;
logic vx_dram_rd_req_fire; logic vx_dram_rd_req_fire;
`DEBUG_BEGIN
logic vx_dram_wr_req_fire; logic vx_dram_wr_req_fire;
`DEBUG_END
logic vx_dram_rd_rsp_fire; logic vx_dram_rd_rsp_fire;
t_local_mem_byte_mask vx_dram_req_byteen_; t_local_mem_byte_mask vx_dram_req_byteen_;
@@ -315,15 +341,17 @@ logic [DRAM_ADDR_WIDTH-1:0] cci_dram_rd_req_addr, cci_dram_wr_req_addr;
logic cci_dram_rd_req_enable, cci_dram_wr_req_enable; logic cci_dram_rd_req_enable, cci_dram_wr_req_enable;
logic vx_dram_req_enable, vx_dram_rd_req_enable, vx_dram_wr_req_enable; logic vx_dram_req_enable, vx_dram_rd_req_enable, vx_dram_wr_req_enable;
logic [DRAM_ADDR_WIDTH-1:0] cci_dram_rd_req_ctr, cci_dram_wr_req_ctr;
assign vortex_enabled = (STATE_RUN == state) || (STATE_CLFLUSH == state); assign vortex_enabled = (STATE_RUN == state) || (STATE_CLFLUSH == state);
assign cci_dram_rd_req_enable = (state == STATE_READ) assign cci_dram_rd_req_enable = (state == STATE_READ)
&& (avs_pending_reads < AVS_RD_QUEUE_SIZE) && (avs_pending_reads < AVS_RD_QUEUE_SIZE)
&& (avs_rd_req_ctr != 0); && (cci_dram_rd_req_ctr != 0);
assign cci_dram_wr_req_enable = (state == STATE_WRITE) assign cci_dram_wr_req_enable = (state == STATE_WRITE)
&& !cci_rdq_empty && !cci_rdq_empty
&& (avs_wr_req_ctr != 0); && (cci_dram_wr_req_ctr < csr_data_size);
assign vx_dram_req_enable = vortex_enabled && (avs_pending_reads < AVS_RD_QUEUE_SIZE); assign vx_dram_req_enable = vortex_enabled && (avs_pending_reads < AVS_RD_QUEUE_SIZE);
assign vx_dram_rd_req_enable = vx_dram_req_enable && vx_dram_req_valid && ~vx_dram_req_rw; assign vx_dram_rd_req_enable = vx_dram_req_enable && vx_dram_req_valid && ~vx_dram_req_rw;
@@ -338,24 +366,22 @@ assign vx_dram_wr_req_fire = vx_dram_wr_req_enable && ~avs_waitrequest;
assign vx_dram_rd_rsp_fire = vx_dram_rsp_valid && vx_dram_rsp_ready; assign vx_dram_rd_rsp_fire = vx_dram_rsp_valid && vx_dram_rsp_ready;
assign avs_pending_reads_next = avs_pending_reads assign avs_pending_reads_next = avs_pending_reads
+ ((cci_dram_rd_req_fire || vx_dram_rd_req_fire) && ~avs_rdq_pop) ? 1 : + (((cci_dram_rd_req_fire || vx_dram_rd_req_fire) && ~avs_rdq_pop) ? 1 :
(~(cci_dram_rd_req_fire || vx_dram_rd_req_fire) && avs_rdq_pop) ? -1 : 0; (~(cci_dram_rd_req_fire || vx_dram_rd_req_fire) && avs_rdq_pop) ? -1 : 0);
assign cmd_write_done = (0 == avs_wr_req_ctr);
if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin
assign vx_dram_req_offset = {{VX_DRAM_LINE_LW{1'b0}}, vx_dram_req_addr[(DRAM_LINE_LW-VX_DRAM_LINE_LW)-1:0]} << VX_DRAM_LINE_LW; assign vx_dram_req_offset = ((DRAM_LINE_LW)'(vx_dram_req_addr[(DRAM_LINE_LW-VX_DRAM_LINE_LW)-1:0])) << VX_DRAM_LINE_LW;
assign vx_dram_req_byteen_ = vx_dram_req_byteen << ({(VX_DRAM_LINE_LW - 3)'(0), vx_dram_req_addr[(DRAM_LINE_LW-VX_DRAM_LINE_LW)-1:0]} << (VX_DRAM_LINE_LW - 3)); assign vx_dram_req_byteen_ = 64'(vx_dram_req_byteen) << (6'(vx_dram_req_addr[(DRAM_LINE_LW-VX_DRAM_LINE_LW)-1:0]) << (VX_DRAM_LINE_LW - 3));
end else begin end else begin
assign vx_dram_req_offset = 0; assign vx_dram_req_offset = 0;
assign vx_dram_req_byteen_ = 64'hffffffffffffffff; assign vx_dram_req_byteen_ = vx_dram_req_byteen;
end end
always_comb always_comb
begin begin
case (state) case (state)
CMD_TYPE_READ: avs_address = cci_dram_rd_req_addr; CMD_TYPE_READ: avs_address = cci_dram_rd_req_addr;
CMD_TYPE_WRITE: avs_address = cci_dram_wr_req_addr; CMD_TYPE_WRITE: avs_address = cci_dram_wr_req_addr + ((DRAM_ADDR_WIDTH)'(t_cci_rdq_tag'(cci_rdq_dout)));
default: avs_address = `VX_TO_DRAM_ADDR(vx_dram_req_addr); default: avs_address = `VX_TO_DRAM_ADDR(vx_dram_req_addr);
endcase endcase
@@ -367,51 +393,53 @@ begin
case (state) case (state)
CMD_TYPE_WRITE: avs_writedata = cci_rdq_dout[$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:$bits(t_cci_rdq_tag)]; CMD_TYPE_WRITE: avs_writedata = cci_rdq_dout[$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:$bits(t_cci_rdq_tag)];
default: avs_writedata = vx_dram_req_data << vx_dram_req_offset; default: avs_writedata = (DRAM_LINE_WIDTH)'(vx_dram_req_data) << vx_dram_req_offset;
endcase endcase
end end
assign avs_read = cci_dram_rd_req_enable || vx_dram_rd_req_enable; assign avs_read = cci_dram_rd_req_enable || vx_dram_rd_req_enable;
assign avs_write = cci_dram_wr_req_enable || vx_dram_wr_req_enable; assign avs_write = cci_dram_wr_req_enable || vx_dram_wr_req_enable;
assign cmd_write_done = (cci_dram_wr_req_ctr >= csr_data_size);
always_ff @(posedge clk) always_ff @(posedge clk)
begin begin
if (SoftReset) if (SoftReset)
begin begin
mem_bank_select <= 0; mem_bank_select <= 0;
avs_burstcount <= 1; avs_burstcount <= 1;
avs_rd_req_ctr <= 0;
avs_wr_req_ctr <= 0;
avs_pending_reads <= 0;
cci_dram_rd_req_addr <= 0; cci_dram_rd_req_addr <= 0;
cci_dram_wr_req_addr <= 0; cci_dram_wr_req_addr <= 0;
cci_dram_rd_req_ctr <= 0;
cci_dram_wr_req_ctr <= 0;
avs_pending_reads <= 0;
end end
else begin else begin
if (state == STATE_IDLE) begin if (state == STATE_IDLE) begin
if (CMD_TYPE_READ == csr_cmd) begin if (CMD_TYPE_READ == csr_cmd) begin
cci_dram_rd_req_addr <= csr_mem_addr; cci_dram_rd_req_addr <= csr_mem_addr;
avs_rd_req_ctr <= csr_data_size; cci_dram_rd_req_ctr <= csr_data_size;
end end
else if (CMD_TYPE_WRITE == csr_cmd) begin else if (CMD_TYPE_WRITE == csr_cmd) begin
cci_dram_wr_req_addr <= csr_mem_addr; cci_dram_wr_req_addr <= csr_mem_addr;
avs_wr_req_ctr <= csr_data_size; cci_dram_wr_req_ctr <= 0;
end end
end end
if (cci_dram_rd_req_fire) begin if (cci_dram_rd_req_fire) begin
cci_dram_rd_req_addr <= cci_dram_rd_req_addr + 1; cci_dram_rd_req_addr <= cci_dram_rd_req_addr + 1;
avs_rd_req_ctr <= avs_rd_req_ctr - 1; cci_dram_rd_req_ctr <= cci_dram_rd_req_ctr - 1;
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
$display("%t: AVS Rd Req: addr=%0h, rem=%0d, pending=%0d", $time, `DRAM_TO_BYTE_ADDR(avs_address), (avs_rd_req_ctr - 1), avs_pending_reads_next); $display("%t: AVS Rd Req: addr=%0h, rem=%0d, pending=%0d", $time, `DRAM_TO_BYTE_ADDR(avs_address), (cci_dram_rd_req_ctr - 1), avs_pending_reads_next);
`endif `endif
end end
if (cci_dram_wr_req_fire) begin if (cci_dram_wr_req_fire) begin
cci_dram_wr_req_addr <= ((cci_dram_wr_req_addr + 1) & ~(CCI_RD_WINDOW_SIZE-1)) | t_cci_rdq_tag'(cci_rdq_dout); cci_dram_wr_req_addr <= cci_dram_wr_req_addr + ((t_cci_rdq_tag'(cci_dram_wr_req_ctr) == (DRAM_ADDR_WIDTH)'(CCI_RD_WINDOW_SIZE-1)) ? (DRAM_ADDR_WIDTH)'(CCI_RD_WINDOW_SIZE) : 0);
avs_wr_req_ctr <= avs_wr_req_ctr - 1; cci_dram_wr_req_ctr <= cci_dram_wr_req_ctr + 1;
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
$display("%t: AVS Wr Req: addr=%0h, data=%0h, rem=%0d", $time, `DRAM_TO_BYTE_ADDR(avs_address), avs_writedata, (avs_wr_req_ctr - 1)); $display("%t: AVS Wr Req: addr=%0h, data=%0h, rem=%0d", $time, `DRAM_TO_BYTE_ADDR(avs_address), avs_writedata, (cci_dram_wr_req_ctr + 1));
`endif `endif
end end
@@ -441,7 +469,7 @@ assign vx_dram_req_ready = vx_dram_req_enable && !avs_waitrequest;
assign vx_dram_rsp_valid = vortex_enabled && !avs_rdq_empty; assign vx_dram_rsp_valid = vortex_enabled && !avs_rdq_empty;
if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin
assign vx_dram_rsp_data = (avs_rdq_dout >> vx_dram_rsp_offset); assign vx_dram_rsp_data = (`VX_DRAM_LINE_WIDTH)'(avs_rdq_dout >> vx_dram_rsp_offset);
end else begin end else begin
assign vx_dram_rsp_data = avs_rdq_dout; assign vx_dram_rsp_data = avs_rdq_dout;
end end
@@ -462,7 +490,8 @@ VX_generic_queue #(
.pop (avs_rtq_pop), .pop (avs_rtq_pop),
.data_out ({vx_dram_rsp_tag, vx_dram_rsp_offset}), .data_out ({vx_dram_rsp_tag, vx_dram_rsp_offset}),
.empty (avs_rtq_empty), .empty (avs_rtq_empty),
.full (avs_rtq_full) .full (avs_rtq_full),
`UNUSED_PIN (size)
); );
// AVS data read response queue /////////////////////////////////////////////// // AVS data read response queue ///////////////////////////////////////////////
@@ -483,25 +512,27 @@ VX_generic_queue #(
.pop (avs_rdq_pop), .pop (avs_rdq_pop),
.data_out (avs_rdq_dout), .data_out (avs_rdq_dout),
.empty (avs_rdq_empty), .empty (avs_rdq_empty),
.full (avs_rdq_full) .full (avs_rdq_full),
`UNUSED_PIN (size)
); );
// CCI-P Read Request /////////////////////////////////////////////////////////// // CCI-P Read Request ///////////////////////////////////////////////////////////
logic [$clog2(CCI_RD_QUEUE_SIZE+1)-1:0] cci_pending_reads, cci_pending_reads_next; logic [$clog2(CCI_RD_QUEUE_SIZE+1)-1:0] cci_pending_reads, cci_pending_reads_next;
t_ccip_clAddr cci_rd_req_addr, cci_rd_req_ctr, cci_rd_req_ctr_next; logic [DRAM_ADDR_WIDTH-1:0] cci_rd_req_ctr, cci_rd_req_ctr_next;
t_ccip_clAddr cci_rd_req_addr;
t_cci_rdq_tag cci_rd_rsp_ctr; t_cci_rdq_tag cci_rd_rsp_ctr;
logic cci_rd_req_fire, cci_rd_rsp_fire; logic cci_rd_req_fire, cci_rd_rsp_fire;
logic cci_rd_req_enable, cci_rd_req_wait; logic cci_rd_req_enable, cci_rd_req_wait;
logic cci_rdq_full, cci_rdq_push, cci_rdq_pop; logic cci_rdq_push, cci_rdq_pop;
t_cci_rdq_data cci_rdq_din; t_cci_rdq_data cci_rdq_din;
always_comb begin always_comb begin
af2cp_sTxPort.c0.hdr = t_ccip_c0_ReqMemHdr'(0); af2cp_sTxPort.c0.hdr = t_ccip_c0_ReqMemHdr'(0);
af2cp_sTxPort.c0.hdr.address = cci_rd_req_addr; af2cp_sTxPort.c0.hdr.address = cci_rd_req_addr;
af2cp_sTxPort.c0.hdr.mdata = t_cci_rdq_tag'(cci_rd_req_ctr); af2cp_sTxPort.c0.hdr.mdata = t_ccip_mdata'(t_cci_rdq_tag'(cci_rd_req_ctr));
end end
assign cci_rd_req_fire = af2cp_sTxPort.c0.valid && !cp2af_sRxPort.c0TxAlmFull; assign cci_rd_req_fire = af2cp_sTxPort.c0.valid && !cp2af_sRxPort.c0TxAlmFull;
@@ -514,8 +545,8 @@ assign cci_rdq_push = cci_rd_rsp_fire;
assign cci_rdq_din = {cp2af_sRxPort.c0.data, t_cci_rdq_tag'(cp2af_sRxPort.c0.hdr.mdata)}; assign cci_rdq_din = {cp2af_sRxPort.c0.data, t_cci_rdq_tag'(cp2af_sRxPort.c0.hdr.mdata)};
assign cci_pending_reads_next = cci_pending_reads assign cci_pending_reads_next = cci_pending_reads
+ (cci_rd_req_fire && ~cci_rdq_pop) ? 1 : + ((cci_rd_req_fire && ~cci_rdq_pop) ? 1 :
(~cci_rd_req_fire && cci_rdq_pop) ? -1 : 0; (~cci_rd_req_fire && cci_rdq_pop) ? -1 : 0);
assign af2cp_sTxPort.c0.valid = cci_rd_req_enable && ~cci_rd_req_wait; assign af2cp_sTxPort.c0.valid = cci_rd_req_enable && ~cci_rd_req_wait;
@@ -549,7 +580,7 @@ begin
if (cci_rd_req_fire) begin if (cci_rd_req_fire) begin
cci_rd_req_addr <= cci_rd_req_addr + 1; cci_rd_req_addr <= cci_rd_req_addr + 1;
cci_rd_req_ctr <= cci_rd_req_ctr_next; cci_rd_req_ctr <= cci_rd_req_ctr_next;
if (t_cci_rdq_tag'(cci_rd_req_ctr) == (CCI_RD_WINDOW_SIZE-1)) begin if (t_cci_rdq_tag'(cci_rd_req_ctr) == t_cci_rdq_tag'(CCI_RD_WINDOW_SIZE-1)) begin
cci_rd_req_wait <= 1; // end current request batch cci_rd_req_wait <= 1; // end current request batch
end end
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
@@ -559,7 +590,7 @@ begin
if (cci_rd_rsp_fire) begin if (cci_rd_rsp_fire) begin
cci_rd_rsp_ctr <= cci_rd_rsp_ctr + 1; cci_rd_rsp_ctr <= cci_rd_rsp_ctr + 1;
if (cci_rd_rsp_ctr == (CCI_RD_WINDOW_SIZE-1)) begin if (cci_rd_rsp_ctr == t_cci_rdq_tag'(CCI_RD_WINDOW_SIZE-1)) begin
cci_rd_req_wait <= 0; // restart new request batch cci_rd_req_wait <= 0; // restart new request batch
end end
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
@@ -589,12 +620,14 @@ VX_generic_queue #(
.pop (cci_rdq_pop), .pop (cci_rdq_pop),
.data_out (cci_rdq_dout), .data_out (cci_rdq_dout),
.empty (cci_rdq_empty), .empty (cci_rdq_empty),
.full (cci_rdq_full) `UNUSED_PIN (full),
`UNUSED_PIN (size)
); );
// CCI-P Write Request ////////////////////////////////////////////////////////// // CCI-P Write Request //////////////////////////////////////////////////////////
logic [$clog2(CCI_RW_QUEUE_SIZE+1)-1:0] cci_pending_writes, cci_pending_writes_next; logic [$clog2(CCI_RW_QUEUE_SIZE+1)-1:0] cci_pending_writes, cci_pending_writes_next;
logic [DRAM_ADDR_WIDTH-1:0] cci_wr_req_ctr;
t_ccip_clAddr cci_wr_req_addr; t_ccip_clAddr cci_wr_req_addr;
logic cci_wr_req_enable, cci_wr_rsp_fire; logic cci_wr_req_enable, cci_wr_rsp_fire;
@@ -609,8 +642,8 @@ assign cci_wr_req_fire = af2cp_sTxPort.c1.valid && !cp2af_sRxPort.c1TxAlmFull;
assign cci_wr_rsp_fire = (STATE_READ == state) && cp2af_sRxPort.c1.rspValid; assign cci_wr_rsp_fire = (STATE_READ == state) && cp2af_sRxPort.c1.rspValid;
assign cci_pending_writes_next = cci_pending_writes assign cci_pending_writes_next = cci_pending_writes
+ (cci_wr_req_fire && ~cci_wr_rsp_fire) ? 1 : + ((cci_wr_req_fire && ~cci_wr_rsp_fire) ? 1 :
(~cci_wr_req_fire && cci_wr_rsp_fire) ? -1 : 0; (~cci_wr_req_fire && cci_wr_rsp_fire) ? -1 : 0);
assign cmd_read_done = (0 == cci_wr_req_ctr) && (0 == cci_pending_writes); assign cmd_read_done = (0 == cci_wr_req_ctr) && (0 == cci_pending_writes);
@@ -660,7 +693,8 @@ end
logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_size; logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_size;
logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_baseaddr; logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_baseaddr;
logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_ctr, snp_rsp_ctr; logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_ctr, snp_req_ctr_next;
logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_rsp_ctr, snp_rsp_ctr_next;
logic vx_snp_req_fire, vx_snp_rsp_fire; logic vx_snp_req_fire, vx_snp_rsp_fire;
@@ -674,6 +708,10 @@ end
assign vx_snp_req_fire = vx_snp_req_valid && vx_snp_req_ready; assign vx_snp_req_fire = vx_snp_req_valid && vx_snp_req_ready;
assign vx_snp_rsp_fire = vx_snp_rsp_valid && vx_snp_rsp_ready; assign vx_snp_rsp_fire = vx_snp_rsp_valid && vx_snp_rsp_ready;
assign snp_req_ctr_next = vx_snp_req_fire ? (snp_req_ctr + 1) : snp_req_ctr;
assign snp_rsp_ctr_next = vx_snp_rsp_fire ? (snp_rsp_ctr - 1) : snp_rsp_ctr;
assign cmd_clflush_done = (0 == snp_rsp_ctr); assign cmd_clflush_done = (0 == snp_rsp_ctr);
always_ff @(posedge clk) always_ff @(posedge clk)
@@ -691,38 +729,40 @@ begin
if ((STATE_IDLE == state) if ((STATE_IDLE == state)
&& (CMD_TYPE_CLFLUSH == csr_cmd)) begin && (CMD_TYPE_CLFLUSH == csr_cmd)) begin
vx_snp_req_addr <= snp_req_baseaddr; vx_snp_req_addr <= snp_req_baseaddr;
snp_req_ctr <= snp_req_size; vx_snp_req_tag <= 0;
snp_req_ctr <= 0;
snp_rsp_ctr <= snp_req_size; snp_rsp_ctr <= snp_req_size;
vx_snp_req_valid <= (snp_req_size != 0); vx_snp_req_valid <= (snp_req_size != 0);
vx_snp_rsp_ready <= (snp_req_size != 0); vx_snp_rsp_ready <= (snp_req_size != 0);
end end
if ((STATE_CLFLUSH == state) if ((STATE_CLFLUSH == state)
&& (0 == snp_rsp_ctr)) begin && (snp_req_ctr_next >= snp_req_size)) begin
vx_snp_rsp_ready <= 0; vx_snp_req_valid <= 0;
end end
if ((STATE_CLFLUSH == state) if ((STATE_CLFLUSH == state)
&& (0 == snp_req_ctr)) begin && (0 == snp_rsp_ctr_next)) begin
vx_snp_req_valid <= 0; vx_snp_rsp_ready <= 0;
end end
if (vx_snp_req_fire) if (vx_snp_req_fire)
begin begin
assert(snp_req_ctr < snp_req_size);
vx_snp_req_addr <= vx_snp_req_addr + 1; vx_snp_req_addr <= vx_snp_req_addr + 1;
vx_snp_req_tag <= snp_req_ctr[`VX_SNP_TAG_WIDTH-1:0]; vx_snp_req_tag <= (`VX_SNP_TAG_WIDTH)'(snp_req_ctr_next);
snp_req_ctr <= snp_req_ctr - 1; snp_req_ctr <= snp_req_ctr_next;
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
$display("%t: AFU Snp Req: addr=%0h, tag=%0d, rem=%0d", $time, `DRAM_TO_BYTE_ADDR(vx_snp_req_addr), vx_snp_req_tag, (snp_req_ctr - 1)); $display("%t: AFU Snp Req: addr=%0h, tag=%0d, rem=%0d", $time, `DRAM_TO_BYTE_ADDR(vx_snp_req_addr), (`VX_SNP_TAG_WIDTH)'(snp_req_ctr_next), (snp_req_size - snp_req_ctr_next));
`endif `endif
end end
if ((STATE_CLFLUSH == state) if ((STATE_CLFLUSH == state)
&& vx_snp_rsp_fire) begin && vx_snp_rsp_fire) begin
assert(snp_rsp_ctr != 0); assert(snp_rsp_ctr != 0);
snp_rsp_ctr <= snp_rsp_ctr - 1; snp_rsp_ctr <= snp_rsp_ctr_next;
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
$display("%t: AFU Snp Rsp: tag=%0d, rem=%0d", $time, vx_snp_rsp_tag, (snp_rsp_ctr - 1)); $display("%t: AFU Snp Rsp: tag=%0d, rem=%0d", $time, vx_snp_rsp_tag, snp_rsp_ctr_next);
`endif `endif
end end
end end
@@ -730,6 +770,8 @@ end
// Vortex binding ///////////////////////////////////////////////////////////// // Vortex binding /////////////////////////////////////////////////////////////
assign cmd_run_done = !vx_busy;
Vortex_Socket #() vx_socket ( Vortex_Socket #() vx_socket (
.clk (clk), .clk (clk),
.reset (vx_reset), .reset (vx_reset),
@@ -761,23 +803,23 @@ Vortex_Socket #() vx_socket (
.snp_rsp_ready (vx_snp_rsp_ready), .snp_rsp_ready (vx_snp_rsp_ready),
// I/O request // I/O request
.io_req_valid (), `UNUSED_PIN (io_req_valid),
.io_req_rw (), `UNUSED_PIN (io_req_rw),
.io_req_byteen (), `UNUSED_PIN (io_req_byteen),
.io_req_addr (), `UNUSED_PIN (io_req_addr),
.io_req_data (), `UNUSED_PIN (io_req_data),
.io_req_tag (), `UNUSED_PIN (io_req_tag),
.io_req_ready (1), .io_req_ready (1),
// I/O response // I/O response
.io_rsp_valid (0), .io_rsp_valid (0),
.io_rsp_data (0), .io_rsp_data (0),
.io_rsp_tag (0), .io_rsp_tag (0),
.io_rsp_ready (), `UNUSED_PIN (io_rsp_ready),
// status // status
.busy (vx_busy), .busy (vx_busy),
.ebreak () `UNUSED_PIN (ebreak)
); );
endmodule endmodule

32
hw/rtl/VX_config.vh
View File

@@ -12,7 +12,7 @@
`endif `endif
`ifndef NUM_WARPS `ifndef NUM_WARPS
`define NUM_WARPS 8 `define NUM_WARPS 4
`endif `endif
`ifndef NUM_THREADS `ifndef NUM_THREADS
@@ -87,7 +87,7 @@
// Number of banks {1, 2, 4, 8,...} // Number of banks {1, 2, 4, 8,...}
`ifndef DNUM_BANKS `ifndef DNUM_BANKS
`define DNUM_BANKS 8 `define DNUM_BANKS 4
`endif `endif
// Size of a word in bytes // Size of a word in bytes
@@ -107,12 +107,12 @@
// Miss Reserv Queue Knob // Miss Reserv Queue Knob
`ifndef DMRVQ_SIZE `ifndef DMRVQ_SIZE
`define DMRVQ_SIZE (`NUM_WARPS*`NUM_THREADS) `define DMRVQ_SIZE `MAX(`NUM_WARPS*`NUM_THREADS, 8)
`endif `endif
// Dram Fill Rsp Queue Size // Dram Fill Rsp Queue Size
`ifndef DDFPQ_SIZE `ifndef DDFPQ_SIZE
`define DDFPQ_SIZE 32 `define DDFPQ_SIZE 16
`endif `endif
// Snoop Req Queue Size // Snoop Req Queue Size
@@ -137,7 +137,7 @@
// Prefetcher // Prefetcher
`ifndef DPRFQ_SIZE `ifndef DPRFQ_SIZE
`define DPRFQ_SIZE 32 `define DPRFQ_SIZE 16
`endif `endif
`ifndef DPRFQ_STRIDE `ifndef DPRFQ_STRIDE
@@ -178,12 +178,12 @@
// Miss Reserv Queue Knob // Miss Reserv Queue Knob
`ifndef IMRVQ_SIZE `ifndef IMRVQ_SIZE
`define IMRVQ_SIZE `ICREQ_SIZE `define IMRVQ_SIZE `MAX(`ICREQ_SIZE, 8)
`endif `endif
// Dram Fill Rsp Queue Size // Dram Fill Rsp Queue Size
`ifndef IDFPQ_SIZE `ifndef IDFPQ_SIZE
`define IDFPQ_SIZE 32 `define IDFPQ_SIZE 16
`endif `endif
// Core Writeback Queue Size // Core Writeback Queue Size
@@ -203,7 +203,7 @@
// Prefetcher // Prefetcher
`ifndef IPRFQ_SIZE `ifndef IPRFQ_SIZE
`define IPRFQ_SIZE 32 `define IPRFQ_SIZE 16
`endif `endif
`ifndef IPRFQ_STRIDE `ifndef IPRFQ_STRIDE
@@ -276,17 +276,17 @@
// Core Request Queue Size // Core Request Queue Size
`ifndef L2CREQ_SIZE `ifndef L2CREQ_SIZE
`define L2CREQ_SIZE 32 `define L2CREQ_SIZE 16
`endif `endif
// Miss Reserv Queue Knob // Miss Reserv Queue Knob
`ifndef L2MRVQ_SIZE `ifndef L2MRVQ_SIZE
`define L2MRVQ_SIZE 32 `define L2MRVQ_SIZE `MAX(`L2CREQ_SIZE, 8)
`endif `endif
// Dram Fill Rsp Queue Size // Dram Fill Rsp Queue Size
`ifndef L2DFPQ_SIZE `ifndef L2DFPQ_SIZE
`define L2DFPQ_SIZE 32 `define L2DFPQ_SIZE 16
`endif `endif
// Snoop Req Queue Size // Snoop Req Queue Size
@@ -311,7 +311,7 @@
// Prefetcher // Prefetcher
`ifndef L2PRFQ_SIZE `ifndef L2PRFQ_SIZE
`define L2PRFQ_SIZE 32 `define L2PRFQ_SIZE 16
`endif `endif
`ifndef L2PRFQ_STRIDE `ifndef L2PRFQ_STRIDE
@@ -347,17 +347,17 @@
// Core Request Queue Size // Core Request Queue Size
`ifndef L3CREQ_SIZE `ifndef L3CREQ_SIZE
`define L3CREQ_SIZE 32 `define L3CREQ_SIZE 16
`endif `endif
// Miss Reserv Queue Knob // Miss Reserv Queue Knob
`ifndef L3MRVQ_SIZE `ifndef L3MRVQ_SIZE
`define L3MRVQ_SIZE `L3CREQ_SIZE `define L3MRVQ_SIZE `MAX(`L3CREQ_SIZE, 8)
`endif `endif
// Dram Fill Rsp Queue Size // Dram Fill Rsp Queue Size
`ifndef L3DFPQ_SIZE `ifndef L3DFPQ_SIZE
`define L3DFPQ_SIZE 32 `define L3DFPQ_SIZE 16
`endif `endif
// Snoop Req Queue Size // Snoop Req Queue Size
@@ -382,7 +382,7 @@
// Prefetcher // Prefetcher
`ifndef L3PRFQ_SIZE `ifndef L3PRFQ_SIZE
`define L3PRFQ_SIZE 32 `define L3PRFQ_SIZE 16
`endif `endif
`ifndef L3PRFQ_STRIDE `ifndef L3PRFQ_STRIDE

1
hw/rtl/VX_define.vh
View File

@@ -48,6 +48,7 @@
`define CLOG2(x) $clog2(x) `define CLOG2(x) $clog2(x)
`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0)) `define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0))
`define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1) `define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1)
`define ISPOW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1))))
`define MIN(x, y) ((x < y) ? (x) : (y)) `define MIN(x, y) ((x < y) ? (x) : (y))
`define MAX(x, y) ((x > y) ? (x) : (y)) `define MAX(x, y) ((x > y) ? (x) : (y))

14
hw/rtl/VX_dmem_ctrl.v
View File

@@ -60,13 +60,13 @@ module VX_dmem_ctrl # (
.NUM_REQUESTS (`SNUM_REQUESTS), .NUM_REQUESTS (`SNUM_REQUESTS),
.STAGE_1_CYCLES (`SSTAGE_1_CYCLES), .STAGE_1_CYCLES (`SSTAGE_1_CYCLES),
.CREQ_SIZE (`SCREQ_SIZE), .CREQ_SIZE (`SCREQ_SIZE),
.MRVQ_SIZE (1), .MRVQ_SIZE (8),
.DFPQ_SIZE (0), .DFPQ_SIZE (1),
.SNRQ_SIZE (0), .SNRQ_SIZE (1),
.CWBQ_SIZE (`SCWBQ_SIZE), .CWBQ_SIZE (`SCWBQ_SIZE),
.DWBQ_SIZE (0), .DWBQ_SIZE (1),
.DFQQ_SIZE (0), .DFQQ_SIZE (1),
.PRFQ_SIZE (0), .PRFQ_SIZE (1),
.PRFQ_STRIDE (0), .PRFQ_STRIDE (0),
.SNOOP_FORWARDING (0), .SNOOP_FORWARDING (0),
.DRAM_ENABLE (0), .DRAM_ENABLE (0),
@@ -223,7 +223,7 @@ module VX_dmem_ctrl # (
.CREQ_SIZE (`ICREQ_SIZE), .CREQ_SIZE (`ICREQ_SIZE),
.MRVQ_SIZE (`IMRVQ_SIZE), .MRVQ_SIZE (`IMRVQ_SIZE),
.DFPQ_SIZE (`IDFPQ_SIZE), .DFPQ_SIZE (`IDFPQ_SIZE),
.SNRQ_SIZE (0), .SNRQ_SIZE (1),
.CWBQ_SIZE (`ICWBQ_SIZE), .CWBQ_SIZE (`ICWBQ_SIZE),
.DWBQ_SIZE (`IDWBQ_SIZE), .DWBQ_SIZE (`IDWBQ_SIZE),
.DFQQ_SIZE (`IDFQQ_SIZE), .DFQQ_SIZE (`IDFQQ_SIZE),

2
hw/rtl/VX_lsu_unit.v
View File

@@ -70,7 +70,7 @@ module VX_lsu_unit #(
for (i = 0; i < `NUM_THREADS; ++i) begin for (i = 0; i < `NUM_THREADS; ++i) begin
assign mem_req_addr[i] = use_address[i][31:2]; assign mem_req_addr[i] = use_address[i][31:2];
assign mem_req_offset[i] = {3'b0, use_address[i][1:0]} << 3; assign mem_req_offset[i] = (5'(use_address[i][1:0])) << 3;
assign mem_req_byteen[i] = (wmask << use_address[i][1:0]); assign mem_req_byteen[i] = (wmask << use_address[i][1:0]);
assign mem_req_data[i] = (use_store_data[i] << mem_req_offset[i]); assign mem_req_data[i] = (use_store_data[i] << mem_req_offset[i]);
end end

2
hw/rtl/Vortex.v
View File

@@ -122,7 +122,7 @@ module Vortex #(
assign io_req_tag = io_core_req_if.core_req_tag[0]; assign io_req_tag = io_core_req_if.core_req_tag[0];
assign io_core_req_if.core_req_ready = io_req_ready; assign io_core_req_if.core_req_ready = io_req_ready;
assign io_core_rsp_if.core_rsp_valid = {{`NUM_THREADS-1{1'b0}}, io_rsp_valid}; assign io_core_rsp_if.core_rsp_valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid};
assign io_core_rsp_if.core_rsp_data[0] = io_rsp_data; assign io_core_rsp_if.core_rsp_data[0] = io_rsp_data;
assign io_core_rsp_if.core_rsp_tag = io_rsp_tag; assign io_core_rsp_if.core_rsp_tag = io_rsp_tag;
assign io_rsp_ready = io_core_rsp_if.core_rsp_ready; assign io_rsp_ready = io_core_rsp_if.core_rsp_ready;

54
hw/rtl/cache/VX_bank.v vendored
View File

@@ -230,7 +230,7 @@ module VX_bank #(
wire mrvq_valid_st0; wire mrvq_valid_st0;
wire[`REQS_BITS-1:0] mrvq_tid_st0; wire[`REQS_BITS-1:0] mrvq_tid_st0;
wire [`LINE_ADDR_WIDTH-1:0] mrvq_addr_st0; wire [`LINE_ADDR_WIDTH-1:0] mrvq_addr_st0;
wire [`WORD_SELECT_WIDTH-1:0] mrvq_wsel_st0; wire [`UP(`WORD_SELECT_WIDTH)-1:0] mrvq_wsel_st0;
wire [`WORD_WIDTH-1:0] mrvq_writeword_st0; wire [`WORD_WIDTH-1:0] mrvq_writeword_st0;
wire [`REQ_TAG_WIDTH-1:0] mrvq_tag_st0; wire [`REQ_TAG_WIDTH-1:0] mrvq_tag_st0;
wire mrvq_rw_st0; wire mrvq_rw_st0;
@@ -287,7 +287,7 @@ module VX_bank #(
wire qual_is_fill_st0; wire qual_is_fill_st0;
wire qual_valid_st0; wire qual_valid_st0;
wire [`LINE_ADDR_WIDTH-1:0] qual_addr_st0; wire [`LINE_ADDR_WIDTH-1:0] qual_addr_st0;
wire [`WORD_SELECT_WIDTH-1:0] qual_wsel_st0; wire [`UP(`WORD_SELECT_WIDTH)-1:0] qual_wsel_st0;
wire qual_from_mrvq_st0; wire qual_from_mrvq_st0;
wire [`WORD_WIDTH-1:0] qual_writeword_st0; wire [`WORD_WIDTH-1:0] qual_writeword_st0;
@@ -298,7 +298,7 @@ module VX_bank #(
wire valid_st1 [STAGE_1_CYCLES-1:0]; wire valid_st1 [STAGE_1_CYCLES-1:0];
wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0]; wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_SELECT_WIDTH-1:0] wsel_st1 [STAGE_1_CYCLES-1:0]; wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0]; wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0];
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0]; wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0];
@@ -313,18 +313,22 @@ module VX_bank #(
mrvq_pop_unqual ? mrvq_addr_st0 : mrvq_pop_unqual ? mrvq_addr_st0 :
reqq_pop_unqual ? reqq_req_addr_st0[`LINE_SELECT_ADDR_RNG] : reqq_pop_unqual ? reqq_req_addr_st0[`LINE_SELECT_ADDR_RNG] :
snrq_pop_unqual ? snrq_addr_st0 : snrq_pop_unqual ? snrq_addr_st0 :
0; 0;
if (`WORD_SELECT_WIDTH != 0) begin
assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`WORD_SELECT_WIDTH-1:0] : assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`WORD_SELECT_WIDTH-1:0] :
mrvq_pop_unqual ? mrvq_wsel_st0 : mrvq_pop_unqual ? mrvq_wsel_st0 :
0; 0;
end else begin
`UNUSED_VAR(mrvq_wsel_st0)
assign qual_wsel_st0 = 0;
end
assign qual_writedata_st0 = dfpq_pop_unqual ? dfpq_filldata_st0 : 57; assign qual_writedata_st0 = dfpq_pop_unqual ? dfpq_filldata_st0 : 57;
assign qual_inst_meta_st0 = mrvq_pop_unqual ? {`REQ_TAG_WIDTH'(mrvq_tag_st0) , mrvq_rw_st0, mrvq_byteen_st0, mrvq_tid_st0} : assign qual_inst_meta_st0 = mrvq_pop_unqual ? {`REQ_TAG_WIDTH'(mrvq_tag_st0) , mrvq_rw_st0, mrvq_byteen_st0, mrvq_tid_st0} :
reqq_pop_unqual ? {`REQ_TAG_WIDTH'(reqq_req_tag_st0), reqq_req_rw_st0, reqq_req_byteen_st0, reqq_req_tid_st0} : reqq_pop_unqual ? {`REQ_TAG_WIDTH'(reqq_req_tag_st0), reqq_req_rw_st0, reqq_req_byteen_st0, reqq_req_tid_st0} :
snrq_pop_unqual ? {`REQ_TAG_WIDTH'(snrq_tag_st0), 1'b0, WORD_SIZE'(0), `REQS_BITS'(0)} : snrq_pop_unqual ? {`REQ_TAG_WIDTH'(snrq_tag_st0), 1'b0, WORD_SIZE'(0), `REQS_BITS'(0)} :
0; 0;
assign qual_going_to_write_st0 = dfpq_pop_unqual ? 1 : assign qual_going_to_write_st0 = dfpq_pop_unqual ? 1 :
(mrvq_pop_unqual && mrvq_rw_st0) ? 1 : (mrvq_pop_unqual && mrvq_rw_st0) ? 1 :
@@ -333,11 +337,11 @@ module VX_bank #(
assign qual_is_snp_st0 = mrvq_pop_unqual ? mrvq_is_snp_st0 : assign qual_is_snp_st0 = mrvq_pop_unqual ? mrvq_is_snp_st0 :
snrq_pop_unqual ? 1 : snrq_pop_unqual ? 1 :
0; 0;
assign qual_writeword_st0 = mrvq_pop_unqual ? mrvq_writeword_st0 : assign qual_writeword_st0 = mrvq_pop_unqual ? mrvq_writeword_st0 :
reqq_pop_unqual ? reqq_req_writeword_st0 : reqq_pop_unqual ? reqq_req_writeword_st0 :
0; 0;
assign qual_from_mrvq_st0 = mrvq_pop_unqual; assign qual_from_mrvq_st0 = mrvq_pop_unqual;
@@ -348,7 +352,7 @@ module VX_bank #(
) )
VX_generic_register #( VX_generic_register #(
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
) s0_1_c0 ( ) s0_1_c0 (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -361,7 +365,7 @@ module VX_bank #(
genvar i; genvar i;
for (i = 1; i < STAGE_1_CYCLES; i++) begin for (i = 1; i < STAGE_1_CYCLES; i++) begin
VX_generic_register #( VX_generic_register #(
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
) s0_1_cc ( ) s0_1_cc (
.clk (clk), .clk (clk),
.reset(reset), .reset(reset),
@@ -428,7 +432,7 @@ module VX_bank #(
.valid_req_st1e (valid_st1e), .valid_req_st1e (valid_st1e),
.writefill_st1e (is_fill_st1[STAGE_1_CYCLES-1]), .writefill_st1e (is_fill_st1[STAGE_1_CYCLES-1]),
.writeaddr_st1e (addr_st1[STAGE_1_CYCLES-1]), .writeaddr_st1e (addr_st1[STAGE_1_CYCLES-1]),
.writewsel_st1e (wsel_st1[STAGE_1_CYCLES-1]), .wordsel_st1e (wsel_st1[STAGE_1_CYCLES-1]),
.writeword_st1e (writeword_st1[STAGE_1_CYCLES-1]), .writeword_st1e (writeword_st1[STAGE_1_CYCLES-1]),
.writedata_st1e (writedata_st1[STAGE_1_CYCLES-1]), .writedata_st1e (writedata_st1[STAGE_1_CYCLES-1]),
@@ -458,7 +462,7 @@ module VX_bank #(
wire from_mrvq_st1e_st2 = from_mrvq_st1e && !is_snp_st1e; wire from_mrvq_st1e_st2 = from_mrvq_st1e && !is_snp_st1e;
wire valid_st2; wire valid_st2;
wire [`WORD_SELECT_WIDTH-1:0] wsel_st2; wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st2;
wire [`WORD_WIDTH-1:0] writeword_st2; wire [`WORD_WIDTH-1:0] writeword_st2;
wire [`WORD_WIDTH-1:0] readword_st2; wire [`WORD_WIDTH-1:0] readword_st2;
wire [`BANK_LINE_WIDTH-1:0] readdata_st2; wire [`BANK_LINE_WIDTH-1:0] readdata_st2;
@@ -478,7 +482,7 @@ module VX_bank #(
wire mrvq_init_ready_state_hazard_st1e_st1; wire mrvq_init_ready_state_hazard_st1e_st1;
VX_generic_register #( VX_generic_register #(
.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH) .N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
) st_1e_2 ( ) st_1e_2 (
.clk (clk), .clk (clk),
.reset(reset), .reset(reset),
@@ -512,7 +516,7 @@ module VX_bank #(
assign recover_mrvq_state_st2 = miss_add && from_mrvq_st2; assign recover_mrvq_state_st2 = miss_add && from_mrvq_st2;
wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr = addr_st2; wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr = addr_st2;
wire [`WORD_SELECT_WIDTH-1:0] miss_add_wsel = wsel_st2; wire [`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel = wsel_st2;
wire [`WORD_WIDTH-1:0] miss_add_data = writeword_st2; wire [`WORD_WIDTH-1:0] miss_add_data = writeword_st2;
assign {miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_tid} = inst_meta_st2; assign {miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_tid} = inst_meta_st2;
wire miss_add_is_snp = is_snp_st2; wire miss_add_is_snp = is_snp_st2;
@@ -718,12 +722,12 @@ module VX_bank #(
`ifdef DBG_PRINT_CACHE_BANK `ifdef DBG_PRINT_CACHE_BANK
if (NUM_BANKS == 1) begin if (NUM_BANKS == 1) begin
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
/*if (core_req_valid && core_req_ready) begin if (core_req_valid && core_req_ready) begin
$display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(core_req_addr), core_req_tag); $display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(core_req_addr), core_req_tag);
end end
if (core_rsp_valid && core_rsp_ready) begin if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data); $display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end*/ end
if (dram_fill_req_valid && dram_fill_req_ready) begin if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_req_addr)); $display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_req_addr));
end end
@@ -733,21 +737,21 @@ module VX_bank #(
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_rsp_addr), dram_fill_rsp_data); $display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_rsp_addr), dram_fill_rsp_data);
end end
/*if (snp_req_valid && snp_req_ready) begin if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(snp_req_addr), snp_req_tag); $display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(snp_req_addr), snp_req_tag);
end end
if (snp_rsp_valid && snp_rsp_ready) begin if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag); $display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end*/ end
end end
end else begin end else begin
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
/*if ((|core_req_valid) && core_req_ready) begin if ((|core_req_valid) && core_req_ready) begin
$display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr, BANK_ID), core_req_tag); $display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr, BANK_ID), core_req_tag);
end end
if (core_rsp_valid && core_rsp_ready) begin if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data); $display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end*/ end
if (dram_fill_req_valid && dram_fill_req_ready) begin if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID)); $display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end end
@@ -757,12 +761,12 @@ module VX_bank #(
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data); $display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end end
/*if (snp_req_valid && snp_req_ready) begin if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_tag); $display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_tag);
end end
if (snp_rsp_valid && snp_rsp_ready) begin if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag); $display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end*/ end
end end
end end
`endif `endif

4
hw/rtl/cache/VX_cache.v vendored
View File

@@ -126,12 +126,12 @@ module VX_cache #(
`DEBUG_BLOCK( `DEBUG_BLOCK(
wire[31:0] debug_core_req_use_pc; wire[31:0] debug_core_req_use_pc;
wire[1:0] debug_core_req_wb; wire[1:0] debug_core_req_wb;
wire[2:0] debug_core_req_rmask;
wire[4:0] debug_core_req_rd; wire[4:0] debug_core_req_rd;
wire[`NW_BITS-1:0] debug_core_req_warp_num; wire[`NW_BITS-1:0] debug_core_req_warp_num;
wire[`LOG2UP(CREQ_SIZE)-1:0] debug_core_req_idx;
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rmask, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0]; assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num, debug_core_req_idx} = core_req_tag[0];
end end
) )
wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid; wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid;

6
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -8,8 +8,8 @@
// tag rw byteen tid // tag rw byteen tid
`define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS) `define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS)
// data metadata word_sel is_snp // data metadata word_sel is_snp
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `WORD_SELECT_WIDTH + 1) `define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH) + 1)
`define REQS_BITS `LOG2UP(NUM_REQUESTS) `define REQS_BITS `LOG2UP(NUM_REQUESTS)
@@ -48,7 +48,7 @@
`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END) `define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END)
`define TAG_SELECT_ADDR_END 31 `define TAG_SELECT_ADDR_END 31
`define WORD_SELECT_WIDTH `LOG2UP(`BANK_LINE_WORDS) `define WORD_SELECT_WIDTH `CLOG2(`BANK_LINE_WORDS)
`define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE)) `define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE))

3
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
View File

@@ -46,6 +46,7 @@ module VX_cache_core_rsp_merge #(
assign core_rsp_tag = per_bank_core_rsp_tag[main_bank_index]; assign core_rsp_tag = per_bank_core_rsp_tag[main_bank_index];
always @(*) begin always @(*) begin
core_rsp_valid = 0; core_rsp_valid = 0;
core_rsp_data = 0;
for (i = 0; i < NUM_BANKS; i++) begin for (i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i] if (per_bank_core_rsp_valid[i]
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin && (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin
@@ -60,6 +61,8 @@ module VX_cache_core_rsp_merge #(
end else begin end else begin
always @(*) begin always @(*) begin
core_rsp_valid = 0; core_rsp_valid = 0;
core_rsp_data = 0;
core_rsp_tag = 0;
for (i = 0; i < NUM_BANKS; i++) begin for (i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i] if (per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]] && !core_rsp_valid[per_bank_core_rsp_tid[i]]

8
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -25,7 +25,7 @@ module VX_cache_miss_resrv #(
input wire miss_add, input wire miss_add,
input wire from_mrvq, input wire from_mrvq,
input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr, input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
input wire[`WORD_SELECT_WIDTH-1:0] miss_add_wsel, input wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel,
input wire[`WORD_WIDTH-1:0] miss_add_data, input wire[`WORD_WIDTH-1:0] miss_add_data,
input wire[`REQS_BITS-1:0] miss_add_tid, input wire[`REQS_BITS-1:0] miss_add_tid,
input wire[`REQ_TAG_WIDTH-1:0] miss_add_tag, input wire[`REQ_TAG_WIDTH-1:0] miss_add_tag,
@@ -46,7 +46,7 @@ module VX_cache_miss_resrv #(
input wire miss_resrv_pop, input wire miss_resrv_pop,
output wire miss_resrv_valid_st0, output wire miss_resrv_valid_st0,
output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0, output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0,
output wire[`WORD_SELECT_WIDTH-1:0] miss_resrv_wsel_st0, output wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_resrv_wsel_st0,
output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0, output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0,
output wire[`REQS_BITS-1:0] miss_resrv_tid_st0, output wire[`REQS_BITS-1:0] miss_resrv_tid_st0,
output wire[`REQ_TAG_WIDTH-1:0] miss_resrv_tag_st0, output wire[`REQ_TAG_WIDTH-1:0] miss_resrv_tag_st0,
@@ -64,8 +64,10 @@ module VX_cache_miss_resrv #(
reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size; reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;
`STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size");
assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE)); assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5)); assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-1));
wire enqueue_possible = !miss_resrv_full; wire enqueue_possible = !miss_resrv_full;
wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;

2
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -97,7 +97,7 @@ module VX_snp_forwarder #(
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
fwdin_sel <= 0; fwdin_sel <= 0;
end else begin end else if (NUM_REQUESTS > 1) begin
fwdin_sel <= fwdin_sel + 1; fwdin_sel <= fwdin_sel + 1;
end end
end end

20
hw/rtl/cache/VX_tag_data_access.v vendored
View File

@@ -38,7 +38,7 @@ module VX_tag_data_access #(
`IGNORE_WARNINGS_BEGIN `IGNORE_WARNINGS_BEGIN
input wire mem_rw_st1e, input wire mem_rw_st1e,
input wire[WORD_SIZE-1:0] mem_byteen_st1e, input wire[WORD_SIZE-1:0] mem_byteen_st1e,
input wire[`WORD_SELECT_WIDTH-1:0] writewsel_st1e, input wire[`UP(`WORD_SELECT_WIDTH)-1:0] wordsel_st1e,
`IGNORE_WARNINGS_END `IGNORE_WARNINGS_END
output wire[`WORD_WIDTH-1:0] readword_st1e, output wire[`WORD_WIDTH-1:0] readword_st1e,
@@ -136,12 +136,16 @@ module VX_tag_data_access #(
end end
assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || ~DRAM_ENABLE; // If shared memory, always valid assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || ~DRAM_ENABLE; // If shared memory, always valid
assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && DRAM_ENABLE; // Dirty only applies in Dcache assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && DRAM_ENABLE && WRITE_ENABLE; // Dirty only applies in Dcache
assign use_read_tag_st1e = DRAM_ENABLE ? read_tag_st1c[STAGE_1_CYCLES-1] : writetag_st1e; // Tag is always the same in SM assign use_read_tag_st1e = DRAM_ENABLE ? read_tag_st1c[STAGE_1_CYCLES-1] : writetag_st1e; // Tag is always the same in SM
assign use_read_dirtyb_st1e= read_dirtyb_st1c[STAGE_1_CYCLES-1]; assign use_read_dirtyb_st1e= read_dirtyb_st1c[STAGE_1_CYCLES-1];
assign use_read_data_st1e = read_data_st1c[STAGE_1_CYCLES-1]; assign use_read_data_st1e = read_data_st1c[STAGE_1_CYCLES-1];
assign readword_st1e = use_read_data_st1e[writewsel_st1e * `WORD_WIDTH +: `WORD_WIDTH]; if (`WORD_SELECT_WIDTH != 0) begin
assign readword_st1e = use_read_data_st1e[wordsel_st1e * `WORD_WIDTH +: `WORD_WIDTH];
end else begin
assign readword_st1e = use_read_data_st1e;
end
wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] we; wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] we;
wire [`BANK_LINE_WIDTH-1:0] data_write; wire [`BANK_LINE_WIDTH-1:0] data_write;
@@ -150,15 +154,15 @@ module VX_tag_data_access #(
&& valid_req_st1e && valid_req_st1e
&& use_read_valid_st1e && use_read_valid_st1e
&& !miss_st1e && !miss_st1e
&& !is_snp_st1e; && !is_snp_st1e
&& !real_writefill;
for (i = 0; i < `BANK_LINE_WORDS; i++) begin for (i = 0; i < `BANK_LINE_WORDS; i++) begin
wire normal_write = ((writewsel_st1e == `WORD_SELECT_WIDTH'(i)) || (`BANK_LINE_WORDS == 1)) wire normal_write = ((`WORD_SELECT_WIDTH == 0) || (wordsel_st1e == `UP(`WORD_SELECT_WIDTH)'(i)))
&& should_write && should_write;
&& !real_writefill;
assign we[i] = real_writefill ? {WORD_SIZE{1'b1}} : assign we[i] = real_writefill ? {WORD_SIZE{1'b1}} :
normal_write ? mem_byteen_st1e: normal_write ? mem_byteen_st1e :
{WORD_SIZE{1'b0}}; {WORD_SIZE{1'b0}};
assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = real_writefill ? writedata_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_st1e; assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = real_writefill ? writedata_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_st1e;

3
hw/rtl/cache/VX_tag_data_structure.v vendored
View File

@@ -33,7 +33,7 @@ module VX_tag_data_structure #(
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0][7:0] data [`BANK_LINE_COUNT-1:0]; reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0]; reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] dirtyb[`BANK_LINE_COUNT-1:0]; reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] dirtyb[`BANK_LINE_COUNT-1:0];
reg dirty[`BANK_LINE_COUNT-1:0]; reg [`BANK_LINE_COUNT-1:0] dirty;
reg [`BANK_LINE_COUNT-1:0] valid; reg [`BANK_LINE_COUNT-1:0] valid;
assign read_valid = valid [read_addr]; assign read_valid = valid [read_addr];
@@ -49,6 +49,7 @@ module VX_tag_data_structure #(
if (reset) begin if (reset) begin
for (i = 0; i < `BANK_LINE_COUNT; i++) begin for (i = 0; i < `BANK_LINE_COUNT; i++) begin
valid[i] <= 0; valid[i] <= 0;
dirty[i] <= 0;
end end
end else if (!stall_bank_pipe) begin end else if (!stall_bank_pipe) begin
if (do_write) begin if (do_write) begin

220
hw/rtl/libs/VX_generic_queue.v
View File

@@ -15,20 +15,42 @@ module VX_generic_queue #(
output wire full, output wire full,
output wire [`LOG2UP(SIZE+1)-1:0] size output wire [`LOG2UP(SIZE+1)-1:0] size
); );
if (SIZE == 0) begin `STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!");
assign empty = 1; reg [`LOG2UP(SIZE+1)-1:0] size_r;
assign data_out = 0; wire reading;
assign full = 0; wire writing;
assign size = 0;
`UNUSED_VAR (clk) assign reading = pop && !empty;
`UNUSED_VAR (reset) assign writing = push && !full;
`UNUSED_VAR (push)
`UNUSED_VAR (pop)
`UNUSED_VAR (data_in)
end else begin // (SIZE > 0) if (SIZE == 1) begin // (SIZE == 1)
reg [DATAW-1:0] head_r;
always @(posedge clk) begin
if (reset) begin
head_r <= 0;
size_r <= 0;
end else begin
if (writing && !reading) begin
size_r <= 1;
end else if (reading && !writing) begin
size_r <= 0;
end
if (writing) begin
head_r <= data_in;
end
end
end
assign data_out = head_r;
assign empty = (size_r == 0);
assign full = (size_r != 0);
assign size = size_r;
end else begin // (SIZE > 1)
`ifdef QUEUE_FORCE_MLAB `ifdef QUEUE_FORCE_MLAB
(* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0]; (* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0];
@@ -36,137 +58,107 @@ module VX_generic_queue #(
reg [DATAW-1:0] data [SIZE-1:0]; reg [DATAW-1:0] data [SIZE-1:0];
`endif `endif
reg [`LOG2UP(SIZE+1)-1:0] size_r; if (0 == BUFFERED_OUTPUT) begin
wire reading;
wire writing;
assign reading = pop && !empty; reg [`LOG2UP(SIZE):0] wr_ptr_r;
assign writing = push && !full; reg [`LOG2UP(SIZE):0] rd_ptr_r;
if (SIZE == 1) begin // (SIZE == 1) wire [`LOG2UP(SIZE)-1:0] wr_ptr_a = wr_ptr_r[`LOG2UP(SIZE)-1:0];
wire [`LOG2UP(SIZE)-1:0] rd_ptr_a = rd_ptr_r[`LOG2UP(SIZE)-1:0];
reg [DATAW-1:0] head_r;
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
head_r <= 0; rd_ptr_r <= 0;
size_r <= 0; wr_ptr_r <= 0;
size_r <= 0;
end else begin end else begin
if (writing && !reading) begin if (writing) begin
size_r <= 1; data[wr_ptr_a] <= data_in;
end else if (reading && !writing) begin wr_ptr_r <= wr_ptr_r + 1;
size_r <= 0;
if (!reading) begin
size_r <= size_r + 1;
end
end end
if (writing) begin if (reading) begin
head_r <= data_in; rd_ptr_r <= rd_ptr_r + 1;
if (!writing) begin
size_r <= size_r - 1;
end
end end
end end
end end
assign data_out = head_r; assign data_out = data[rd_ptr_a];
assign empty = (size_r == 0); assign empty = (wr_ptr_r == rd_ptr_r);
assign full = (size_r != 0); assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[`LOG2UP(SIZE)] != rd_ptr_r[`LOG2UP(SIZE)]);
assign size = size_r; assign size = size_r;
end else begin // (SIZE > 1) end else begin
if (0 == BUFFERED_OUTPUT) begin reg [DATAW-1:0] head_r;
reg [DATAW-1:0] curr_r;
reg [`LOG2UP(SIZE)-1:0] wr_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_next_r;
reg empty_r;
reg full_r;
reg bypass_r;
reg [`LOG2UP(SIZE):0] wr_ptr_r; always @(posedge clk) begin
reg [`LOG2UP(SIZE):0] rd_ptr_r; if (reset) begin
wr_ptr_r <= 0;
rd_ptr_r <= 0;
rd_ptr_next_r <= 1;
empty_r <= 1;
full_r <= 0;
size_r <= 0;
end else begin
if (writing) begin
data[wr_ptr_r] <= data_in;
wr_ptr_r <= wr_ptr_r + 1;
wire [`LOG2UP(SIZE)-1:0] wr_ptr_a = wr_ptr_r[`LOG2UP(SIZE)-1:0]; if (!reading) begin
wire [`LOG2UP(SIZE)-1:0] rd_ptr_a = rd_ptr_r[`LOG2UP(SIZE)-1:0]; empty_r <= 0;
if (size_r == SIZE-1) begin
always @(posedge clk) begin full_r <= 1;
if (reset) begin
rd_ptr_r <= 0;
wr_ptr_r <= 0;
size_r <= 0;
end else begin
if (writing) begin
data[wr_ptr_a] <= data_in;
wr_ptr_r <= wr_ptr_r + 1;
if (!reading) begin
size_r <= size_r + 1;
end
end
if (reading) begin
rd_ptr_r <= rd_ptr_r + 1;
if (!writing) begin
size_r <= size_r - 1;
end end
size_r <= size_r + 1;
end end
end end
end
assign data_out = data[rd_ptr_a]; if (reading) begin
assign empty = (wr_ptr_r == rd_ptr_r); rd_ptr_r <= rd_ptr_next_r;
assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[`LOG2UP(SIZE)] != rd_ptr_r[`LOG2UP(SIZE)]);
assign size = size_r;
end else begin if (SIZE > 2) begin
rd_ptr_next_r <= rd_ptr_r + 2;
reg [DATAW-1:0] head_r; end else begin // (SIZE == 2);
reg [DATAW-1:0] curr_r; rd_ptr_next_r <= ~rd_ptr_next_r;
reg [`LOG2UP(SIZE)-1:0] wr_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_next_r;
reg empty_r;
reg full_r;
reg bypass_r;
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
empty_r <= 1;
full_r <= 0;
wr_ptr_r <= 0;
rd_ptr_r <= 0;
rd_ptr_next_r <= 1;
end else begin
if (writing) begin
data[wr_ptr_r] <= data_in;
wr_ptr_r <= wr_ptr_r + 1;
if (!reading) begin
empty_r <= 0;
if (size_r == $bits(size_r)'(SIZE-1)) begin
full_r <= 1;
end
size_r <= size_r + 1;
end
end end
if (reading) begin if (!writing) begin
rd_ptr_r <= rd_ptr_next_r; if (size_r == 1) begin
if (SIZE == 2) begin assert(rd_ptr_next_r == wr_ptr_r);
rd_ptr_next_r <= ~rd_ptr_next_r; empty_r <= 1;
end else if (SIZE > 2) begin end;
rd_ptr_next_r <= rd_ptr_r + 2; full_r <= 0;
end size_r <= size_r - 1;
if (!writing) begin
if (size_r == 1) begin
empty_r <= 1;
end;
full_r <= 0;
size_r <= size_r - 1;
end
end end
bypass_r <= writing && (empty_r || (1 == size_r) && reading);
curr_r <= data_in;
head_r <= data[reading ? rd_ptr_next_r : rd_ptr_r];
end end
end
assign data_out = bypass_r ? curr_r : head_r; bypass_r <= writing
assign empty = empty_r; && (empty_r || ((1 == size_r) && reading)); // empty or about to go empty
assign full = full_r;
assign size = size_r; curr_r <= data_in;
head_r <= data[reading ? rd_ptr_next_r : rd_ptr_r];
end
end end
assign data_out = bypass_r ? curr_r : head_r;
assign empty = empty_r;
assign full = full_r;
assign size = size_r;
end end
end end

3
hw/simulate/simulator.cpp
View File

@@ -11,8 +11,7 @@ double sc_time_stamp() {
Simulator::Simulator() { Simulator::Simulator() {
// force random values for unitialized signals // force random values for unitialized signals
const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+50"}; Verilated::randReset(2);
Verilated::commandArgs(3, args);
ram_ = nullptr; ram_ = nullptr;
vortex_ = new VVortex_Socket(); vortex_ = new VVortex_Socket();

8
hw/syn/quartus/top/Makefile
View File

@@ -1,6 +1,6 @@
PROJECT = Vortex_Socket PROJECT = vortex_afu
TOP_LEVEL_ENTITY = Vortex_Socket TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = Vortex_Socket.v SRC_FILE = vortex_afu.sv
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Part, Family # Part, Family
@@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES)
# Project initialization # Project initialization
$(PROJECT_FILES): $(PROJECT_FILES):
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache;../../../opae"
syn.chg: syn.chg:
$(STAMP) syn.chg $(STAMP) syn.chg

0
hw/syn/quartus/top/vortex.sdc → hw/syn/quartus/top/project.sdc
View File

6
hw/syn/quartus/vortex/Makefile
View File

@@ -1,6 +1,6 @@
PROJECT = Vortex PROJECT = Vortex_Socket
TOP_LEVEL_ENTITY = Vortex TOP_LEVEL_ENTITY = Vortex_Socket
SRC_FILE = Vortex.v SRC_FILE = Vortex_Socket.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Part, Family # Part, Family

0
hw/syn/quartus/vortex/vortex.sdc → hw/syn/quartus/vortex/project.sdc
View File

3
hw/syn/quartus/vortex/timing.tcl
View File

@@ -1,4 +1,4 @@
project_open Vortex project_open Vortex_Socket
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
@@ -6,7 +6,6 @@ create_timing_netlist
read_sdc read_sdc
update_timing_netlist update_timing_netlist
foreach_in_collection op [get_available_operating_conditions] { foreach_in_collection op [get_available_operating_conditions] {
set_operating_conditions $op set_operating_conditions $op