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This commit is contained in:
Blaise Tine
2020-06-03 06:25:34 -04:00
parent 106d707024 04fc34b848
commit 626a4f6fc1
27 changed files with 383 additions and 314 deletions
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32
hw/rtl/VX_config.vh
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@@ -12,7 +12,7 @@
`endif
`ifndef NUM_WARPS
`define NUM_WARPS 8
`define NUM_WARPS 4
`endif
`ifndef NUM_THREADS
@@ -87,7 +87,7 @@
// Number of banks {1, 2, 4, 8,...}
`ifndef DNUM_BANKS
`define DNUM_BANKS 8
`define DNUM_BANKS 4
`endif
// Size of a word in bytes
@@ -107,12 +107,12 @@
// Miss Reserv Queue Knob
`ifndef DMRVQ_SIZE
`define DMRVQ_SIZE (`NUM_WARPS*`NUM_THREADS)
`define DMRVQ_SIZE `MAX(`NUM_WARPS*`NUM_THREADS, 8)
`endif
// Dram Fill Rsp Queue Size
`ifndef DDFPQ_SIZE
`define DDFPQ_SIZE 32
`define DDFPQ_SIZE 16
`endif
// Snoop Req Queue Size
@@ -137,7 +137,7 @@
// Prefetcher
`ifndef DPRFQ_SIZE
`define DPRFQ_SIZE 32
`define DPRFQ_SIZE 16
`endif
`ifndef DPRFQ_STRIDE
@@ -178,12 +178,12 @@
// Miss Reserv Queue Knob
`ifndef IMRVQ_SIZE
`define IMRVQ_SIZE `ICREQ_SIZE
`define IMRVQ_SIZE `MAX(`ICREQ_SIZE, 8)
`endif
// Dram Fill Rsp Queue Size
`ifndef IDFPQ_SIZE
`define IDFPQ_SIZE 32
`define IDFPQ_SIZE 16
`endif
// Core Writeback Queue Size
@@ -203,7 +203,7 @@
// Prefetcher
`ifndef IPRFQ_SIZE
`define IPRFQ_SIZE 32
`define IPRFQ_SIZE 16
`endif
`ifndef IPRFQ_STRIDE
@@ -276,17 +276,17 @@
// Core Request Queue Size
`ifndef L2CREQ_SIZE
`define L2CREQ_SIZE 32
`define L2CREQ_SIZE 16
`endif
// Miss Reserv Queue Knob
`ifndef L2MRVQ_SIZE
`define L2MRVQ_SIZE 32
`define L2MRVQ_SIZE `MAX(`L2CREQ_SIZE, 8)
`endif
// Dram Fill Rsp Queue Size
`ifndef L2DFPQ_SIZE
`define L2DFPQ_SIZE 32
`define L2DFPQ_SIZE 16
`endif
// Snoop Req Queue Size
@@ -311,7 +311,7 @@
// Prefetcher
`ifndef L2PRFQ_SIZE
`define L2PRFQ_SIZE 32
`define L2PRFQ_SIZE 16
`endif
`ifndef L2PRFQ_STRIDE
@@ -347,17 +347,17 @@
// Core Request Queue Size
`ifndef L3CREQ_SIZE
`define L3CREQ_SIZE 32
`define L3CREQ_SIZE 16
`endif
// Miss Reserv Queue Knob
`ifndef L3MRVQ_SIZE
`define L3MRVQ_SIZE `L3CREQ_SIZE
`define L3MRVQ_SIZE `MAX(`L3CREQ_SIZE, 8)
`endif
// Dram Fill Rsp Queue Size
`ifndef L3DFPQ_SIZE
`define L3DFPQ_SIZE 32
`define L3DFPQ_SIZE 16
`endif
// Snoop Req Queue Size
@@ -382,7 +382,7 @@
// Prefetcher
`ifndef L3PRFQ_SIZE
`define L3PRFQ_SIZE 32
`define L3PRFQ_SIZE 16
`endif
`ifndef L3PRFQ_STRIDE

1
hw/rtl/VX_define.vh
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@@ -48,6 +48,7 @@
`define CLOG2(x) $clog2(x)
`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0))
`define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1)
`define ISPOW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1))))
`define MIN(x, y) ((x < y) ? (x) : (y))
`define MAX(x, y) ((x > y) ? (x) : (y))

14
hw/rtl/VX_dmem_ctrl.v
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@@ -60,13 +60,13 @@ module VX_dmem_ctrl # (
.NUM_REQUESTS (`SNUM_REQUESTS),
.STAGE_1_CYCLES (`SSTAGE_1_CYCLES),
.CREQ_SIZE (`SCREQ_SIZE),
.MRVQ_SIZE (1),
.DFPQ_SIZE (0),
.SNRQ_SIZE (0),
.MRVQ_SIZE (8),
.DFPQ_SIZE (1),
.SNRQ_SIZE (1),
.CWBQ_SIZE (`SCWBQ_SIZE),
.DWBQ_SIZE (0),
.DFQQ_SIZE (0),
.PRFQ_SIZE (0),
.DWBQ_SIZE (1),
.DFQQ_SIZE (1),
.PRFQ_SIZE (1),
.PRFQ_STRIDE (0),
.SNOOP_FORWARDING (0),
.DRAM_ENABLE (0),
@@ -223,7 +223,7 @@ module VX_dmem_ctrl # (
.CREQ_SIZE (`ICREQ_SIZE),
.MRVQ_SIZE (`IMRVQ_SIZE),
.DFPQ_SIZE (`IDFPQ_SIZE),
.SNRQ_SIZE (0),
.SNRQ_SIZE (1),
.CWBQ_SIZE (`ICWBQ_SIZE),
.DWBQ_SIZE (`IDWBQ_SIZE),
.DFQQ_SIZE (`IDFQQ_SIZE),

2
hw/rtl/VX_lsu_unit.v
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@@ -70,7 +70,7 @@ module VX_lsu_unit #(
for (i = 0; i < `NUM_THREADS; ++i) begin
assign mem_req_addr[i] = use_address[i][31:2];
assign mem_req_offset[i] = {3'b0, use_address[i][1:0]} << 3;
assign mem_req_offset[i] = (5'(use_address[i][1:0])) << 3;
assign mem_req_byteen[i] = (wmask << use_address[i][1:0]);
assign mem_req_data[i] = (use_store_data[i] << mem_req_offset[i]);
end

2
hw/rtl/Vortex.v
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@@ -122,7 +122,7 @@ module Vortex #(
assign io_req_tag = io_core_req_if.core_req_tag[0];
assign io_core_req_if.core_req_ready = io_req_ready;
assign io_core_rsp_if.core_rsp_valid = {{`NUM_THREADS-1{1'b0}}, io_rsp_valid};
assign io_core_rsp_if.core_rsp_valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid};
assign io_core_rsp_if.core_rsp_data[0] = io_rsp_data;
assign io_core_rsp_if.core_rsp_tag = io_rsp_tag;
assign io_rsp_ready = io_core_rsp_if.core_rsp_ready;

54
hw/rtl/cache/VX_bank.v vendored
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@@ -230,7 +230,7 @@ module VX_bank #(
wire mrvq_valid_st0;
wire[`REQS_BITS-1:0] mrvq_tid_st0;
wire [`LINE_ADDR_WIDTH-1:0] mrvq_addr_st0;
wire [`WORD_SELECT_WIDTH-1:0] mrvq_wsel_st0;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] mrvq_wsel_st0;
wire [`WORD_WIDTH-1:0] mrvq_writeword_st0;
wire [`REQ_TAG_WIDTH-1:0] mrvq_tag_st0;
wire mrvq_rw_st0;
@@ -287,7 +287,7 @@ module VX_bank #(
wire qual_is_fill_st0;
wire qual_valid_st0;
wire [`LINE_ADDR_WIDTH-1:0] qual_addr_st0;
wire [`WORD_SELECT_WIDTH-1:0] qual_wsel_st0;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] qual_wsel_st0;
wire qual_from_mrvq_st0;
wire [`WORD_WIDTH-1:0] qual_writeword_st0;
@@ -298,7 +298,7 @@ module VX_bank #(
wire valid_st1 [STAGE_1_CYCLES-1:0];
wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_SELECT_WIDTH-1:0] wsel_st1 [STAGE_1_CYCLES-1:0];
wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0];
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0];
@@ -313,18 +313,22 @@ module VX_bank #(
mrvq_pop_unqual ? mrvq_addr_st0 :
reqq_pop_unqual ? reqq_req_addr_st0[`LINE_SELECT_ADDR_RNG] :
snrq_pop_unqual ? snrq_addr_st0 :
0;
assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`WORD_SELECT_WIDTH-1:0] :
mrvq_pop_unqual ? mrvq_wsel_st0 :
0;
0;
if (`WORD_SELECT_WIDTH != 0) begin
assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`WORD_SELECT_WIDTH-1:0] :
mrvq_pop_unqual ? mrvq_wsel_st0 :
0;
end else begin
`UNUSED_VAR(mrvq_wsel_st0)
assign qual_wsel_st0 = 0;
end
assign qual_writedata_st0 = dfpq_pop_unqual ? dfpq_filldata_st0 : 57;
assign qual_inst_meta_st0 = mrvq_pop_unqual ? {`REQ_TAG_WIDTH'(mrvq_tag_st0) , mrvq_rw_st0, mrvq_byteen_st0, mrvq_tid_st0} :
reqq_pop_unqual ? {`REQ_TAG_WIDTH'(reqq_req_tag_st0), reqq_req_rw_st0, reqq_req_byteen_st0, reqq_req_tid_st0} :
snrq_pop_unqual ? {`REQ_TAG_WIDTH'(snrq_tag_st0), 1'b0, WORD_SIZE'(0), `REQS_BITS'(0)} :
0;
0;
assign qual_going_to_write_st0 = dfpq_pop_unqual ? 1 :
(mrvq_pop_unqual && mrvq_rw_st0) ? 1 :
@@ -333,11 +337,11 @@ module VX_bank #(
assign qual_is_snp_st0 = mrvq_pop_unqual ? mrvq_is_snp_st0 :
snrq_pop_unqual ? 1 :
0;
0;
assign qual_writeword_st0 = mrvq_pop_unqual ? mrvq_writeword_st0 :
reqq_pop_unqual ? reqq_req_writeword_st0 :
0;
0;
assign qual_from_mrvq_st0 = mrvq_pop_unqual;
@@ -348,7 +352,7 @@ module VX_bank #(
)
VX_generic_register #(
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
) s0_1_c0 (
.clk (clk),
.reset (reset),
@@ -361,7 +365,7 @@ module VX_bank #(
genvar i;
for (i = 1; i < STAGE_1_CYCLES; i++) begin
VX_generic_register #(
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH)
) s0_1_cc (
.clk (clk),
.reset(reset),
@@ -428,7 +432,7 @@ module VX_bank #(
.valid_req_st1e (valid_st1e),
.writefill_st1e (is_fill_st1[STAGE_1_CYCLES-1]),
.writeaddr_st1e (addr_st1[STAGE_1_CYCLES-1]),
.writewsel_st1e (wsel_st1[STAGE_1_CYCLES-1]),
.wordsel_st1e (wsel_st1[STAGE_1_CYCLES-1]),
.writeword_st1e (writeword_st1[STAGE_1_CYCLES-1]),
.writedata_st1e (writedata_st1[STAGE_1_CYCLES-1]),
@@ -458,7 +462,7 @@ module VX_bank #(
wire from_mrvq_st1e_st2 = from_mrvq_st1e && !is_snp_st1e;
wire valid_st2;
wire [`WORD_SELECT_WIDTH-1:0] wsel_st2;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st2;
wire [`WORD_WIDTH-1:0] writeword_st2;
wire [`WORD_WIDTH-1:0] readword_st2;
wire [`BANK_LINE_WIDTH-1:0] readdata_st2;
@@ -478,7 +482,7 @@ module VX_bank #(
wire mrvq_init_ready_state_hazard_st1e_st1;
VX_generic_register #(
.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
.N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH)
) st_1e_2 (
.clk (clk),
.reset(reset),
@@ -512,7 +516,7 @@ module VX_bank #(
assign recover_mrvq_state_st2 = miss_add && from_mrvq_st2;
wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr = addr_st2;
wire [`WORD_SELECT_WIDTH-1:0] miss_add_wsel = wsel_st2;
wire [`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel = wsel_st2;
wire [`WORD_WIDTH-1:0] miss_add_data = writeword_st2;
assign {miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_tid} = inst_meta_st2;
wire miss_add_is_snp = is_snp_st2;
@@ -718,12 +722,12 @@ module VX_bank #(
`ifdef DBG_PRINT_CACHE_BANK
if (NUM_BANKS == 1) begin
always_ff @(posedge clk) begin
/*if (core_req_valid && core_req_ready) begin
if (core_req_valid && core_req_ready) begin
$display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(core_req_addr), core_req_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end*/
end
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_req_addr));
end
@@ -733,21 +737,21 @@ module VX_bank #(
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_rsp_addr), dram_fill_rsp_data);
end
/*if (snp_req_valid && snp_req_ready) begin
if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(snp_req_addr), snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end*/
end
end
end else begin
always_ff @(posedge clk) begin
/*if ((|core_req_valid) && core_req_ready) begin
if ((|core_req_valid) && core_req_ready) begin
$display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr, BANK_ID), core_req_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end*/
end
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
@@ -757,12 +761,12 @@ module VX_bank #(
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
/*if (snp_req_valid && snp_req_ready) begin
if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end*/
end
end
end
`endif

6
hw/rtl/cache/VX_cache.v vendored
View File

@@ -125,13 +125,13 @@ module VX_cache #(
`DEBUG_BLOCK(
wire[31:0] debug_core_req_use_pc;
wire[1:0] debug_core_req_wb;
wire[2:0] debug_core_req_rmask;
wire[1:0] debug_core_req_wb;
wire[4:0] debug_core_req_rd;
wire[`NW_BITS-1:0] debug_core_req_warp_num;
wire[`LOG2UP(CREQ_SIZE)-1:0] debug_core_req_idx;
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rmask, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0];
assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num, debug_core_req_idx} = core_req_tag[0];
end
)
wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valid;

6
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -8,8 +8,8 @@
// tag rw byteen tid
`define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS)
// data metadata word_sel is_snp
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `WORD_SELECT_WIDTH + 1)
// data metadata word_sel is_snp
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH) + 1)
`define REQS_BITS `LOG2UP(NUM_REQUESTS)
@@ -48,7 +48,7 @@
`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END)
`define TAG_SELECT_ADDR_END 31
`define WORD_SELECT_WIDTH `LOG2UP(`BANK_LINE_WORDS)
`define WORD_SELECT_WIDTH `CLOG2(`BANK_LINE_WORDS)
`define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE))

3
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -46,6 +46,7 @@ module VX_cache_core_rsp_merge #(
assign core_rsp_tag = per_bank_core_rsp_tag[main_bank_index];
always @(*) begin
core_rsp_valid = 0;
core_rsp_data = 0;
for (i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]
&& (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin
@@ -60,6 +61,8 @@ module VX_cache_core_rsp_merge #(
end else begin
always @(*) begin
core_rsp_valid = 0;
core_rsp_data = 0;
core_rsp_tag = 0;
for (i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]]

8
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -25,7 +25,7 @@ module VX_cache_miss_resrv #(
input wire miss_add,
input wire from_mrvq,
input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
input wire[`WORD_SELECT_WIDTH-1:0] miss_add_wsel,
input wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel,
input wire[`WORD_WIDTH-1:0] miss_add_data,
input wire[`REQS_BITS-1:0] miss_add_tid,
input wire[`REQ_TAG_WIDTH-1:0] miss_add_tag,
@@ -46,7 +46,7 @@ module VX_cache_miss_resrv #(
input wire miss_resrv_pop,
output wire miss_resrv_valid_st0,
output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0,
output wire[`WORD_SELECT_WIDTH-1:0] miss_resrv_wsel_st0,
output wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_resrv_wsel_st0,
output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0,
output wire[`REQS_BITS-1:0] miss_resrv_tid_st0,
output wire[`REQ_TAG_WIDTH-1:0] miss_resrv_tag_st0,
@@ -64,8 +64,10 @@ module VX_cache_miss_resrv #(
reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;
`STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size");
assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5));
assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-1));
wire enqueue_possible = !miss_resrv_full;
wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;

2
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -97,7 +97,7 @@ module VX_snp_forwarder #(
always @(posedge clk) begin
if (reset) begin
fwdin_sel <= 0;
end else begin
end else if (NUM_REQUESTS > 1) begin
fwdin_sel <= fwdin_sel + 1;
end
end

20
hw/rtl/cache/VX_tag_data_access.v vendored
View File

@@ -38,7 +38,7 @@ module VX_tag_data_access #(
`IGNORE_WARNINGS_BEGIN
input wire mem_rw_st1e,
input wire[WORD_SIZE-1:0] mem_byteen_st1e,
input wire[`WORD_SELECT_WIDTH-1:0] writewsel_st1e,
input wire[`UP(`WORD_SELECT_WIDTH)-1:0] wordsel_st1e,
`IGNORE_WARNINGS_END
output wire[`WORD_WIDTH-1:0] readword_st1e,
@@ -136,12 +136,16 @@ module VX_tag_data_access #(
end
assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || ~DRAM_ENABLE; // If shared memory, always valid
assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && DRAM_ENABLE; // Dirty only applies in Dcache
assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && DRAM_ENABLE && WRITE_ENABLE; // Dirty only applies in Dcache
assign use_read_tag_st1e = DRAM_ENABLE ? read_tag_st1c[STAGE_1_CYCLES-1] : writetag_st1e; // Tag is always the same in SM
assign use_read_dirtyb_st1e= read_dirtyb_st1c[STAGE_1_CYCLES-1];
assign use_read_data_st1e = read_data_st1c[STAGE_1_CYCLES-1];
assign readword_st1e = use_read_data_st1e[writewsel_st1e * `WORD_WIDTH +: `WORD_WIDTH];
if (`WORD_SELECT_WIDTH != 0) begin
assign readword_st1e = use_read_data_st1e[wordsel_st1e * `WORD_WIDTH +: `WORD_WIDTH];
end else begin
assign readword_st1e = use_read_data_st1e;
end
wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] we;
wire [`BANK_LINE_WIDTH-1:0] data_write;
@@ -150,15 +154,15 @@ module VX_tag_data_access #(
&& valid_req_st1e
&& use_read_valid_st1e
&& !miss_st1e
&& !is_snp_st1e;
&& !is_snp_st1e
&& !real_writefill;
for (i = 0; i < `BANK_LINE_WORDS; i++) begin
wire normal_write = ((writewsel_st1e == `WORD_SELECT_WIDTH'(i)) || (`BANK_LINE_WORDS == 1))
&& should_write
&& !real_writefill;
wire normal_write = ((`WORD_SELECT_WIDTH == 0) || (wordsel_st1e == `UP(`WORD_SELECT_WIDTH)'(i)))
&& should_write;
assign we[i] = real_writefill ? {WORD_SIZE{1'b1}} :
normal_write ? mem_byteen_st1e:
normal_write ? mem_byteen_st1e :
{WORD_SIZE{1'b0}};
assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = real_writefill ? writedata_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_st1e;

3
hw/rtl/cache/VX_tag_data_structure.v vendored
View File

@@ -33,7 +33,7 @@ module VX_tag_data_structure #(
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] dirtyb[`BANK_LINE_COUNT-1:0];
reg dirty[`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_COUNT-1:0] dirty;
reg [`BANK_LINE_COUNT-1:0] valid;
assign read_valid = valid [read_addr];
@@ -49,6 +49,7 @@ module VX_tag_data_structure #(
if (reset) begin
for (i = 0; i < `BANK_LINE_COUNT; i++) begin
valid[i] <= 0;
dirty[i] <= 0;
end
end else if (!stall_bank_pipe) begin
if (do_write) begin

254
hw/rtl/libs/VX_generic_queue.v
View File

@@ -15,158 +15,150 @@ module VX_generic_queue #(
output wire full,
output wire [`LOG2UP(SIZE+1)-1:0] size
);
if (SIZE == 0) begin
`STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!");
assign empty = 1;
assign data_out = 0;
assign full = 0;
assign size = 0;
reg [`LOG2UP(SIZE+1)-1:0] size_r;
wire reading;
wire writing;
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (push)
`UNUSED_VAR (pop)
`UNUSED_VAR (data_in)
assign reading = pop && !empty;
assign writing = push && !full;
if (SIZE == 1) begin // (SIZE == 1)
reg [DATAW-1:0] head_r;
always @(posedge clk) begin
if (reset) begin
head_r <= 0;
size_r <= 0;
end else begin
if (writing && !reading) begin
size_r <= 1;
end else if (reading && !writing) begin
size_r <= 0;
end
if (writing) begin
head_r <= data_in;
end
end
end
assign data_out = head_r;
assign empty = (size_r == 0);
assign full = (size_r != 0);
assign size = size_r;
end else begin // (SIZE > 1)
end else begin // (SIZE > 0)
`ifdef QUEUE_FORCE_MLAB
(* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0];
`else
reg [DATAW-1:0] data [SIZE-1:0];
`endif
reg [`LOG2UP(SIZE+1)-1:0] size_r;
wire reading;
wire writing;
if (0 == BUFFERED_OUTPUT) begin
assign reading = pop && !empty;
assign writing = push && !full;
reg [`LOG2UP(SIZE):0] wr_ptr_r;
reg [`LOG2UP(SIZE):0] rd_ptr_r;
if (SIZE == 1) begin // (SIZE == 1)
reg [DATAW-1:0] head_r;
wire [`LOG2UP(SIZE)-1:0] wr_ptr_a = wr_ptr_r[`LOG2UP(SIZE)-1:0];
wire [`LOG2UP(SIZE)-1:0] rd_ptr_a = rd_ptr_r[`LOG2UP(SIZE)-1:0];
always @(posedge clk) begin
if (reset) begin
head_r <= 0;
size_r <= 0;
rd_ptr_r <= 0;
wr_ptr_r <= 0;
size_r <= 0;
end else begin
if (writing && !reading) begin
size_r <= 1;
end else if (reading && !writing) begin
size_r <= 0;
if (writing) begin
data[wr_ptr_a] <= data_in;
wr_ptr_r <= wr_ptr_r + 1;
if (!reading) begin
size_r <= size_r + 1;
end
end
if (writing) begin
head_r <= data_in;
if (reading) begin
rd_ptr_r <= rd_ptr_r + 1;
if (!writing) begin
size_r <= size_r - 1;
end
end
end
end
assign data_out = data[rd_ptr_a];
assign empty = (wr_ptr_r == rd_ptr_r);
assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[`LOG2UP(SIZE)] != rd_ptr_r[`LOG2UP(SIZE)]);
assign size = size_r;
end else begin
reg [DATAW-1:0] head_r;
reg [DATAW-1:0] curr_r;
reg [`LOG2UP(SIZE)-1:0] wr_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_next_r;
reg empty_r;
reg full_r;
reg bypass_r;
always @(posedge clk) begin
if (reset) begin
wr_ptr_r <= 0;
rd_ptr_r <= 0;
rd_ptr_next_r <= 1;
empty_r <= 1;
full_r <= 0;
size_r <= 0;
end else begin
if (writing) begin
data[wr_ptr_r] <= data_in;
wr_ptr_r <= wr_ptr_r + 1;
if (!reading) begin
empty_r <= 0;
if (size_r == SIZE-1) begin
full_r <= 1;
end
size_r <= size_r + 1;
end
end
if (reading) begin
rd_ptr_r <= rd_ptr_next_r;
if (SIZE > 2) begin
rd_ptr_next_r <= rd_ptr_r + 2;
end else begin // (SIZE == 2);
rd_ptr_next_r <= ~rd_ptr_next_r;
end
if (!writing) begin
if (size_r == 1) begin
assert(rd_ptr_next_r == wr_ptr_r);
empty_r <= 1;
end;
full_r <= 0;
size_r <= size_r - 1;
end
end
bypass_r <= writing
&& (empty_r || ((1 == size_r) && reading)); // empty or about to go empty
curr_r <= data_in;
head_r <= data[reading ? rd_ptr_next_r : rd_ptr_r];
end
end
end
assign data_out = head_r;
assign empty = (size_r == 0);
assign full = (size_r != 0);
assign data_out = bypass_r ? curr_r : head_r;
assign empty = empty_r;
assign full = full_r;
assign size = size_r;
end else begin // (SIZE > 1)
if (0 == BUFFERED_OUTPUT) begin
reg [`LOG2UP(SIZE):0] wr_ptr_r;
reg [`LOG2UP(SIZE):0] rd_ptr_r;
wire [`LOG2UP(SIZE)-1:0] wr_ptr_a = wr_ptr_r[`LOG2UP(SIZE)-1:0];
wire [`LOG2UP(SIZE)-1:0] rd_ptr_a = rd_ptr_r[`LOG2UP(SIZE)-1:0];
always @(posedge clk) begin
if (reset) begin
rd_ptr_r <= 0;
wr_ptr_r <= 0;
size_r <= 0;
end else begin
if (writing) begin
data[wr_ptr_a] <= data_in;
wr_ptr_r <= wr_ptr_r + 1;
if (!reading) begin
size_r <= size_r + 1;
end
end
if (reading) begin
rd_ptr_r <= rd_ptr_r + 1;
if (!writing) begin
size_r <= size_r - 1;
end
end
end
end
assign data_out = data[rd_ptr_a];
assign empty = (wr_ptr_r == rd_ptr_r);
assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[`LOG2UP(SIZE)] != rd_ptr_r[`LOG2UP(SIZE)]);
assign size = size_r;
end else begin
reg [DATAW-1:0] head_r;
reg [DATAW-1:0] curr_r;
reg [`LOG2UP(SIZE)-1:0] wr_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_r;
reg [`LOG2UP(SIZE)-1:0] rd_ptr_next_r;
reg empty_r;
reg full_r;
reg bypass_r;
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
empty_r <= 1;
full_r <= 0;
wr_ptr_r <= 0;
rd_ptr_r <= 0;
rd_ptr_next_r <= 1;
end else begin
if (writing) begin
data[wr_ptr_r] <= data_in;
wr_ptr_r <= wr_ptr_r + 1;
if (!reading) begin
empty_r <= 0;
if (size_r == $bits(size_r)'(SIZE-1)) begin
full_r <= 1;
end
size_r <= size_r + 1;
end
end
if (reading) begin
rd_ptr_r <= rd_ptr_next_r;
if (SIZE == 2) begin
rd_ptr_next_r <= ~rd_ptr_next_r;
end else if (SIZE > 2) begin
rd_ptr_next_r <= rd_ptr_r + 2;
end
if (!writing) begin
if (size_r == 1) begin
empty_r <= 1;
end;
full_r <= 0;
size_r <= size_r - 1;
end
end
bypass_r <= writing && (empty_r || (1 == size_r) && reading);
curr_r <= data_in;
head_r <= data[reading ? rd_ptr_next_r : rd_ptr_r];
end
end
assign data_out = bypass_r ? curr_r : head_r;
assign empty = empty_r;
assign full = full_r;
assign size = size_r;
end
end
end