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fixed several bugs and refactor memory access

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This commit is contained in:
Blaise Tine
2022-02-04 17:50:19 -05:00
parent cf2a0a5f39
commit 5fbace9fa0
13 changed files with 483 additions and 578 deletions
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18
sim/simx/types.h
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@@ -16,21 +16,17 @@ typedef uint32_t Word;
typedef int32_t WordI;
typedef uint64_t DWord;
typedef int64_t DWordI;
typedef uint32_t Addr;
typedef uint32_t Size;
typedef uint32_t FWord;
#elif XLEN == 64
typedef uint64_t Word;
typedef int64_t WordI;
typedef __uint128_t DWord;
typedef __int128_t DWordI;
typedef uint64_t Addr;
typedef uint64_t Size;
typedef uint64_t FWord;
#else
#error unsupported XLEN
#endif
typedef uint64_t FWord;
typedef std::bitset<32> RegMask;
typedef std::bitset<32> ThreadMask;
typedef std::bitset<32> WarpMask;
@@ -44,12 +40,12 @@ enum class RegType {
Vector
};
inline std::ostream &operator<<(std::ostream &os, const RegType& type) {
switch (type) {
inline std::ostream &operator<<(std::ostream &os, const RegType& clss) {
switch (clss) {
case RegType::None: break;
case RegType::Integer: os << "r"; break;
case RegType::Float: os << "fr"; break;
case RegType::Vector: os << "vr"; break;
case RegType::Integer: os << "x"; break;
case RegType::Float: os << "f"; break;
case RegType::Vector: os << "v"; break;
}
return os;
}