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fixed several bugs and refactor memory access

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This commit is contained in:
Blaise Tine
2022-02-04 17:50:19 -05:00
parent cf2a0a5f39
commit 5fbace9fa0
13 changed files with 483 additions and 578 deletions
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280
sim/simx/decode.cpp
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@@ -19,7 +19,7 @@ struct InstTableEntry_t {
InstType iType;
};
static const std::unordered_map<int, struct InstTableEntry_t> sc_instTable = {
static const std::unordered_map<Opcode, struct InstTableEntry_t> sc_instTable = {
{Opcode::NOP, {false, InstType::N_TYPE}},
{Opcode::R_INST, {false, InstType::R_TYPE}},
{Opcode::L_INST, {false, InstType::I_TYPE}},
@@ -42,17 +42,54 @@ static const std::unordered_map<int, struct InstTableEntry_t> sc_instTable = {
{Opcode::VSET, {false, InstType::V_TYPE}},
{Opcode::GPGPU, {false, InstType::R_TYPE}},
{Opcode::GPU, {false, InstType::R4_TYPE}},
{Opcode::R_INST_64, {false, InstType::R_TYPE}},
{Opcode::I_INST_64, {false, InstType::I_TYPE}},
{Opcode::R_INST_W, {false, InstType::R_TYPE}},
{Opcode::I_INST_W, {false, InstType::I_TYPE}},
};
enum Constants {
width_opcode= 7,
width_reg = 5,
width_func2 = 2,
width_func3 = 3,
width_func6 = 6,
width_func7 = 7,
width_mop = 3,
width_vmask = 1,
width_i_imm = 12,
width_j_imm = 20,
width_v_imm = 11,
shift_opcode= 0,
shift_rd = width_opcode,
shift_func3 = shift_rd + width_reg,
shift_rs1 = shift_func3 + width_func3,
shift_rs2 = shift_rs1 + width_reg,
shift_func2 = shift_rs2 + width_reg,
shift_func7 = shift_rs2 + width_reg,
shift_rs3 = shift_func7 + width_func2,
shift_vmop = shift_func7 + width_vmask,
shift_vnf = shift_vmop + width_mop,
shift_func6 = shift_func7 + width_vmask,
shift_vset = shift_func7 + width_func6,
mask_opcode = (1<<width_opcode)-1,
mask_reg = (1<<width_reg)-1,
mask_func2 = (1<<width_func2)-1,
mask_func3 = (1<<width_func3)-1,
mask_func6 = (1<<width_func6)-1,
mask_func7 = (1<<width_func7)-1,
mask_i_imm = (1<<width_i_imm)-1,
mask_j_imm = (1<<width_j_imm)-1,
mask_v_imm = (1<<width_v_imm)-1,
};
static const char* op_string(const Instr &instr) {
auto opcode = instr.getOpcode();
uint32_t func2 = instr.getFunc2();
uint32_t func3 = instr.getFunc3();
uint32_t func7 = instr.getFunc7();
uint32_t rs2 = instr.getRSrc(1);
Word imm = instr.getImm();
auto func2 = instr.getFunc2();
auto func3 = instr.getFunc3();
auto func7 = instr.getFunc7();
auto rs2 = instr.getRSrc(1);
auto imm = instr.getImm();
switch (opcode) {
case Opcode::NOP: return "NOP";
@@ -92,7 +129,7 @@ static const char* op_string(const Instr &instr) {
case 5: return func7 ? "SRAI" : "SRLI";
case 6: return "ORI";
case 7: return "ANDI";
}
}
case Opcode::B_INST:
switch (func3) {
case 0: return "BEQ";
@@ -127,7 +164,7 @@ static const char* op_string(const Instr &instr) {
default:
std::abort();
}
case Opcode::R_INST_64:
case Opcode::R_INST_W:
if (func7 & 0x1){
switch (func3) {
case 0: return "MULW";
@@ -147,7 +184,7 @@ static const char* op_string(const Instr &instr) {
std::abort();
}
}
case Opcode::I_INST_64:
case Opcode::I_INST_W:
switch (func3) {
case 0: return "ADDIW";
case 1: return "SLLIW";
@@ -333,8 +370,8 @@ static const char* op_string(const Instr &instr) {
namespace vortex {
std::ostream &operator<<(std::ostream &os, const Instr &instr) {
auto opcode = instr.getOpcode();
uint32_t func2 = instr.getFunc2();
uint32_t func3 = instr.getFunc3();
auto func2 = instr.getFunc2();
auto func3 = instr.getFunc3();
os << op_string(instr) << ": ";
@@ -368,56 +405,22 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
}
}
Decoder::Decoder(const ArchDef &arch) {
inst_s_ = arch.wsize() * 8;
opcode_s_ = 7;
reg_s_ = 5;
func2_s_ = 2;
func3_s_ = 3;
mop_s_ = 3;
vmask_s_ = 1;
shift_opcode_ = 0;
shift_rd_ = opcode_s_;
shift_func3_ = shift_rd_ + reg_s_;
shift_rs1_ = shift_func3_ + func3_s_;
shift_rs2_ = shift_rs1_ + reg_s_;
shift_func2_ = shift_rs2_ + reg_s_;
shift_func7_ = shift_rs2_ + reg_s_;
shift_rs3_ = shift_func7_ + func2_s_;
shift_vmop_ = shift_func7_ + vmask_s_;
shift_vnf_ = shift_vmop_ + mop_s_;
shift_func6_ = shift_func7_ + 1;
shift_vset_ = shift_func7_ + 6;
reg_mask_ = 0x1f;
func2_mask_ = 0x3;
func3_mask_ = 0x7;
func6_mask_ = 0x3f;
func7_mask_ = 0x7f;
opcode_mask_ = 0x7f;
i_imm_mask_ = 0xfff;
s_imm_mask_ = 0xfff;
b_imm_mask_ = 0x1fff;
u_imm_mask_ = 0xfffff;
j_imm_mask_ = 0xfffff;
v_imm_mask_ = 0x7ff;
}
Decoder::Decoder(const ArchDef&) {}
std::shared_ptr<Instr> Decoder::decode(uint32_t code) const {
auto instr = std::make_shared<Instr>();
Opcode op = (Opcode)((code >> shift_opcode_) & opcode_mask_);
auto op = Opcode((code >> shift_opcode) & mask_opcode);
instr->setOpcode(op);
uint32_t func2 = (code >> shift_func2_) & func2_mask_;
uint32_t func3 = (code >> shift_func3_) & func3_mask_;
uint32_t func6 = (code >> shift_func6_) & func6_mask_;
uint32_t func7 = (code >> shift_func7_) & func7_mask_;
auto func2 = (code >> shift_func2) & mask_func2;
auto func3 = (code >> shift_func3) & mask_func3;
auto func6 = (code >> shift_func6) & mask_func6;
auto func7 = (code >> shift_func7) & mask_func7;
int rd = (code >> shift_rd_) & reg_mask_;
int rs1 = (code >> shift_rs1_) & reg_mask_;
int rs2 = (code >> shift_rs2_) & reg_mask_;
int rs3 = (code >> shift_rs3_) & reg_mask_;
auto rd = (code >> shift_rd) & mask_reg;
auto rs1 = (code >> shift_rs1) & mask_reg;
auto rs2 = (code >> shift_rs2) & mask_reg;
auto rs3 = (code >> shift_rs3) & mask_reg;
auto op_it = sc_instTable.find(op);
if (op_it == sc_instTable.end()) {
@@ -437,45 +440,45 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code) const {
break;
case InstType::R_TYPE:
if (op == Opcode::FCI) {
switch (func7) {
if (op == Opcode::FCI) {
switch (func7) {
case 0x50: // FLE.S, FLT.S, FEQ.S
case 0x51: // FLE.D, FLT.D, FEQ.D
case 0x60: // FCVT.W.D, FCVT.WU.D, FCVT.L.D, FCVT.LU.D
case 0x61: // FCVT.WU.S, FCVT.W.S, FCVT.L.S, FCVT.LU.S
case 0x70: // FCLASS.S, FMV.X.W
case 0x71: // FCLASS.D, FMV.X.D
instr->setDestReg(rd, RegType::Integer);
instr->setSrcReg(rs1, RegType::Float);
break;
case 0x68: // FCVT.S.W, FCVT.S.WU, FCVT.S.L, FCVT.S.LU
case 0x69: // FCVT.D.W, FCVT.D.WU, FCVT.D.L, FCVT.D.LU
case 0x78: // FMV.W.X
case 0x79: // FMV.D.X
instr->setSrcReg(rs1);
case 0x79: // FMV.D.X
instr->setDestReg(rd, RegType::Float);
instr->setSrcReg(rs1, RegType::Integer);
break;
default:
instr->setSrcFReg(rs1);
}
instr->setSrcFReg(rs2);
switch (func7) {
case 0x50: // FLE.S, FLT.S, FEQ.S
case 0x51: // FLE.D, FLT.D, FEQ.D
case 0x60: // FCVT.WU.S, FCVT.W.S, FCVT.L.S, FCVT.LU.S
case 0x61: // FCVT.W.D, FCVT.WU.D, FCVT.L.D, FCVT.LU.D
case 0x70: // FLASS.S, FMV.X.W
case 0x71: // FCLASS.D, FMV.X.D
instr->setDestReg(rd);
instr->setDestReg(rd, RegType::Float);
instr->setSrcReg(rs1, RegType::Float);
instr->setSrcReg(rs2, RegType::Float);
break;
default:
instr->setDestFReg(rd);
}
} else {
instr->setDestReg(rd);
instr->setSrcReg(rs1);
instr->setSrcReg(rs2);
instr->setDestReg(rd, RegType::Integer);
instr->setSrcReg(rs1, RegType::Integer);
instr->setSrcReg(rs2, RegType::Integer);
}
instr->setFunc3(func3);
instr->setFunc7(func7);
break;
case InstType::I_TYPE: {
instr->setSrcReg(rs1);
instr->setSrcReg(rs1, RegType::Integer);
if (op == Opcode::FL) {
instr->setDestFReg(rd);
instr->setDestReg(rd, RegType::Float);
} else {
instr->setDestReg(rd);
instr->setDestReg(rd, RegType::Integer);
}
instr->setFunc3(func3);
instr->setFunc7(func7);
@@ -483,80 +486,71 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code) const {
case Opcode::SYS_INST:
case Opcode::FENCE:
// uint12
instr->setImm(code >> shift_rs2_);
instr->setImm(code >> shift_rs2);
break;
case Opcode::I_INST:
case Opcode::I_INST_W:
if (func3 == 0x1 || func3 == 0x5) {
// int5 (XLEN = 32) / int6 (XLEN = 64)
Word shamt_mask = ((Word)1 << log2up(XLEN)) - 1;
Word shamt = (((func7 & 0x1) << 5) | rs2) & shamt_mask;
auto shamt = rs2; // uint5
#if (XLEN == 64)
if (op == Opcode::I_INST) {
// uint6
shamt |= ((func7 & 0x1) << 5);
}
#endif
instr->setImm(shamt);
} else {
// int12
Word imm = code >> shift_rs2_;
instr->setImm(sext(imm, 12));
}
break;
case Opcode::I_INST_64:
if (func3 == 0x1 || func3 == 0x5) {
// int5
Word shamt = rs2;
instr->setImm(shamt);
} else {
// int12
Word imm = code >> shift_rs2_;
instr->setImm(sext(imm, 12));
auto imm = code >> shift_rs2;
instr->setImm(sext(imm, width_i_imm));
}
break;
default:
// int12
Word imm = code >> shift_rs2_;
instr->setImm(sext(imm, 12));
auto imm = code >> shift_rs2;
instr->setImm(sext(imm, width_i_imm));
break;
}
} break;
case InstType::S_TYPE: {
instr->setSrcReg(rs1);
instr->setSrcReg(rs1, RegType::Integer);
if (op == Opcode::FS) {
instr->setSrcFReg(rs2);
instr->setSrcReg(rs2, RegType::Float);
} else {
instr->setSrcReg(rs2);
instr->setSrcReg(rs2, RegType::Integer);
}
instr->setFunc3(func3);
Word imm = (func7 << reg_s_) | rd;
instr->setImm(sext(imm, 12));
auto imm = (func7 << width_reg) | rd;
instr->setImm(sext(imm, width_i_imm));
} break;
case InstType::B_TYPE: {
instr->setSrcReg(rs1);
instr->setSrcReg(rs2);
instr->setSrcReg(rs1, RegType::Integer);
instr->setSrcReg(rs2, RegType::Integer);
instr->setFunc3(func3);
uint32_t bit_11 = rd & 0x1;
uint32_t bits_4_1 = rd >> 1;
uint32_t bit_10_5 = func7 & 0x3f;
uint32_t bit_12 = func7 >> 6;
Word imm = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
instr->setImm(sext(imm, 13));
auto bit_11 = rd & 0x1;
auto bits_4_1 = rd >> 1;
auto bit_10_5 = func7 & 0x3f;
auto bit_12 = func7 >> 6;
auto imm = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
instr->setImm(sext(imm, width_i_imm+1));
} break;
case InstType::U_TYPE: {
instr->setDestReg(rd);
Word imm = code >> shift_func3_;
instr->setImm(sext(imm, 20));
instr->setDestReg(rd, RegType::Integer);
auto imm = code >> shift_func3;
instr->setImm(sext(imm, width_j_imm));
} break;
case InstType::J_TYPE: {
instr->setDestReg(rd);
uint32_t unordered = code >> shift_func3_;
uint32_t bits_19_12 = unordered & 0xff;
uint32_t bit_11 = (unordered >> 8) & 0x1;
uint32_t bits_10_1 = (unordered >> 9) & 0x3ff;
uint32_t bit_20 = (unordered >> 19) & 0x1;
Word imm = (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
if (bit_20) {
imm |= ~j_imm_mask_;
}
instr->setImm(imm);
instr->setDestReg(rd, RegType::Integer);
auto unordered = code >> shift_func3;
auto bits_19_12 = unordered & 0xff;
auto bit_11 = (unordered >> 8) & 0x1;
auto bits_10_1 = (unordered >> 9) & 0x3ff;
auto bit_20 = (unordered >> 19) & 0x1;
auto imm = (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
instr->setImm(sext(imm, width_j_imm+1));
} break;
case InstType::V_TYPE:
@@ -566,9 +560,9 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code) const {
instr->setSrcVReg(rs1);
instr->setFunc3(func3);
if (func3 == 7) {
instr->setImm(!(code >> shift_vset_));
instr->setImm(!(code >> shift_vset));
if (instr->getImm()) {
uint32_t immed = (code >> shift_rs2_) & v_imm_mask_;
auto immed = (code >> shift_rs2) & mask_v_imm;
instr->setImm(immed);
instr->setVlmul(immed & 0x3);
instr->setVediv((immed >> 4) & 0x3);
@@ -578,7 +572,7 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code) const {
}
} else {
instr->setSrcVReg(rs2);
instr->setVmask((code >> shift_func7_) & 0x1);
instr->setVmask((code >> shift_func7) & 0x1);
instr->setFunc6(func6);
}
} break;
@@ -588,9 +582,9 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code) const {
instr->setSrcVReg(rs1);
instr->setVlsWidth(func3);
instr->setSrcVReg(rs2);
instr->setVmask(code >> shift_func7_);
instr->setVmop((code >> shift_vmop_) & func3_mask_);
instr->setVnf((code >> shift_vnf_) & func3_mask_);
instr->setVmask(code >> shift_func7);
instr->setVmop((code >> shift_vmop) & mask_func3);
instr->setVnf((code >> shift_vnf) & mask_func3);
break;
case Opcode::FS:
@@ -598,9 +592,9 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code) const {
instr->setSrcVReg(rs1);
instr->setVlsWidth(func3);
instr->setSrcVReg(rs2);
instr->setVmask(code >> shift_func7_);
instr->setVmop((code >> shift_vmop_) & func3_mask_);
instr->setVnf((code >> shift_vnf_) & func3_mask_);
instr->setVmask(code >> shift_func7);
instr->setVmop((code >> shift_vmop) & mask_func3);
instr->setVnf((code >> shift_vnf) & mask_func3);
break;
default:
@@ -609,15 +603,15 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code) const {
break;
case R4_TYPE:
if (op == Opcode::GPU) {
instr->setDestReg(rd);
instr->setSrcReg(rs1);
instr->setSrcReg(rs2);
instr->setSrcReg(rs3);
instr->setDestReg(rd, RegType::Integer);
instr->setSrcReg(rs1, RegType::Integer);
instr->setSrcReg(rs2, RegType::Integer);
instr->setSrcReg(rs3, RegType::Integer);
} else {
instr->setDestFReg(rd);
instr->setSrcFReg(rs1);
instr->setSrcFReg(rs2);
instr->setSrcFReg(rs3);
instr->setDestReg(rd, RegType::Float);
instr->setSrcReg(rs1, RegType::Float);
instr->setSrcReg(rs2, RegType::Float);
instr->setSrcReg(rs3, RegType::Float);
}
instr->setFunc2(func2);
instr->setFunc3(func3);