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refactoring

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This commit is contained in:
Blaise Tine
2020-06-23 09:54:40 -07:00
parent 0a01385a2c
commit 5e718c2676
10 changed files with 706 additions and 706 deletions
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8
hw/simulate/simulator.cpp
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@@ -14,7 +14,7 @@ Simulator::Simulator() {
Verilated::randReset(2);
ram_ = nullptr;
vortex_ = new VVortex_Socket();
vortex_ = new VVortex();
dram_rsp_active_ = false;
snp_req_active_ = false;
@@ -241,12 +241,12 @@ bool Simulator::run() {
// check riscv-tests PASSED/FAILED status
#if (NUM_CLUSTERS == 1 && NUM_CORES == 1)
int status = (int)vortex_->Vortex_Socket->genblk1__DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->pipeline->back_end->writeback->last_data_wb & 0xf;
int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf;
#else
#if (NUM_CLUSTERS == 1)
int status = (int)vortex_->Vortex_Socket->genblk1__DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->pipeline->back_end->writeback->last_data_wb & 0xf;
int status = (int)vortex_->Vortex->genblk1__DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf;
#else
int status = (int)vortex_->Vortex_Socket->genblk2__DOT__genblk1__BRA__0__KET____DOT__Vortex_Cluster->genblk1__BRA__0__KET____DOT__vortex_core->pipeline->back_end->writeback->last_data_wb & 0xf;
int status = (int)vortex_->Vortex->genblk2__DOT__genblk1__BRA__0__KET____DOT__cluster->genblk1__BRA__0__KET____DOT__core->pipeline->back_end->writeback->last_data_wb & 0xf;
#endif
#endif

6
hw/simulate/simulator.h
View File

@@ -1,7 +1,7 @@
#pragma once
#include "VVortex_Socket.h"
#include "VVortex_Socket__Syms.h"
#include "VVortex.h"
#include "VVortex__Syms.h"
#include "verilated.h"
#ifdef VCD_OUTPUT
@@ -62,7 +62,7 @@ private:
uint32_t pending_snp_reqs_;
RAM *ram_;
VVortex_Socket *vortex_;
VVortex *vortex_;
#ifdef VCD_OUTPUT
VerilatedVcdC *trace_;
#endif