Gather FPGA perf stats

2020-07-01 09:30:12 -07:00
parent e92029c31a
commit 5d088d67c8
12 changed files with 55 additions and 51 deletions
--- a/hw/rtl/VX_csr_pipe.v
+++ b/hw/rtl/VX_csr_pipe.v
@@ -38,7 +38,6 @@ module VX_csr_pipe #(
        .wb_valid       (| writeback_if.valid)
    );

-    // wire hazard = (csr_address_s2 == csr_req_if.csr_address) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2;
    wire car_hazard = (csr_address_s2 == csr_req_if.csr_address) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2;

    assign csr_read_data = car_hazard ? csr_updated_data_s2 : csr_read_data_unqual;