minor update

hw/rtl/VX_alu_unit.v

@@ -199,4 +199,13 @@ module VX_alu_unit #(
     // can accept new request?
     assign alu_req_if.ready = ~stall_in;
 
+`ifdef DBG_PRINT_PIPELINE
+    always @(posedge clk) begin
+        if (branch_ctl_if.valid) begin
+            $display("%t: core%0d-branch: wid=%0d, PC=%0h, taken=%b, dest=%0h", $time, CORE_ID, 
+                branch_ctl_if.wid, alu_commit_if.PC, branch_ctl_if.taken, branch_ctl_if.dest);
+        end
+    end
+`endif
+
 endmodule

hw/rtl/libs/VX_elastic_buffer.v

@@ -17,6 +17,8 @@ module VX_elastic_buffer #(
     input  wire             ready_out,
     output wire             valid_out
 );
+    `STATIC_ASSERT (SIZE != 1, ("invalid value"))
+
     if (SIZE == 0) begin
 
         `UNUSED_VAR (clk)