dcache response bus optimization

2021-07-12 10:14:48 -07:00
parent b99fb41d52
commit 5c40422e4f
16 changed files with 350 additions and 259 deletions
--- a/hw/rtl/interfaces/VX_dcache_core_rsp_if.v
+++ b/hw/rtl/interfaces/VX_dcache_core_rsp_if.v
@@ -9,10 +9,11 @@ interface VX_dcache_core_rsp_if #(
    parameter CORE_TAG_WIDTH = 1
 ) ();

-    wire [NUM_REQS-1:0]                     valid;    
+    wire                                    valid;
+    wire [NUM_REQS-1:0]                     tmask;
    wire [NUM_REQS-1:0][`WORD_WIDTH-1:0]    data;
-    wire [CORE_TAG_WIDTH-1:0]               tag;    
-    wire                                    ready;      
+    wire [CORE_TAG_WIDTH-1:0]               tag;
+    wire                                    ready;

 endinterface