dcache response bus optimization
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@@ -19,7 +19,8 @@ module VX_pipeline #(
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input wire [`NUM_THREADS-1:0] dcache_req_ready,
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// Dcache core reponse
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input wire [`NUM_THREADS-1:0] dcache_rsp_valid,
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input wire dcache_rsp_valid,
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input wire [`NUM_THREADS-1:0] dcache_rsp_tmask,
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input wire [`NUM_THREADS-1:0][31:0] dcache_rsp_data,
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input wire [`DCORE_TAG_WIDTH-1:0] dcache_rsp_tag,
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output wire dcache_rsp_ready,
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@@ -72,6 +73,7 @@ module VX_pipeline #(
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) dcache_core_rsp_if();
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assign dcache_core_rsp_if.valid = dcache_rsp_valid;
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assign dcache_core_rsp_if.tmask = dcache_rsp_tmask;
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assign dcache_core_rsp_if.data = dcache_rsp_data;
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assign dcache_core_rsp_if.tag = dcache_rsp_tag;
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assign dcache_rsp_ready = dcache_core_rsp_if.ready;
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@@ -130,12 +132,21 @@ module VX_pipeline #(
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VX_perf_pipeline_if perf_pipeline_if();
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`endif
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wire fetch_reset, decode_reset, issue_reset, execute_reset, commit_reset;
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VX_reset_relay #(
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.NUM_NODES (5)
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) reset_relay (
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.clk (clk),
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.reset (reset),
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.reset_o ({fetch_reset, decode_reset, issue_reset, execute_reset, commit_reset})
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);
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VX_fetch #(
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.CORE_ID(CORE_ID)
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) fetch (
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`SCOPE_BIND_VX_pipeline_fetch
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.clk (clk),
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.reset (reset),
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.reset (fetch_reset),
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.icache_req_if (icache_core_req_if),
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.icache_rsp_if (icache_core_rsp_if),
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.wstall_if (wstall_if),
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@@ -150,7 +161,7 @@ module VX_pipeline #(
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.CORE_ID(CORE_ID)
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) decode (
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.clk (clk),
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.reset (reset),
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.reset (decode_reset),
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.ifetch_rsp_if (ifetch_rsp_if),
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.decode_if (decode_if),
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.wstall_if (wstall_if),
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@@ -163,7 +174,7 @@ module VX_pipeline #(
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`SCOPE_BIND_VX_pipeline_issue
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.clk (clk),
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.reset (reset),
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.reset (issue_reset),
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`ifdef PERF_ENABLE
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.perf_pipeline_if (perf_pipeline_if),
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@@ -185,7 +196,7 @@ module VX_pipeline #(
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`SCOPE_BIND_VX_pipeline_execute
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.clk (clk),
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.reset (reset),
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.reset (execute_reset),
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`ifdef PERF_ENABLE
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.perf_memsys_if (perf_memsys_if),
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@@ -219,7 +230,7 @@ module VX_pipeline #(
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.CORE_ID(CORE_ID)
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) commit (
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.clk (clk),
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.reset (reset),
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.reset (commit_reset),
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.alu_commit_if (alu_commit_if),
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.ld_commit_if (ld_commit_if),
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