cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
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@@ -200,6 +200,7 @@ module VX_pipeline #(
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.fpu_commit_if (fpu_commit_if),
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.gpu_commit_if (gpu_commit_if),
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.busy (busy),
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.ebreak (ebreak)
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);
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