cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
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@@ -14,52 +14,52 @@ module VX_io_arb #(
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input wire reset,
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// input requests
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input wire [NUM_REQUESTS-1:0][`NUM_THREADS-1:0] in_io_req_valid,
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input wire [NUM_REQUESTS-1:0] in_io_req_rw,
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input wire [NUM_REQUESTS-1:0][`NUM_THREADS-1:0][WORD_SIZE-1:0] in_io_req_byteen,
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input wire [NUM_REQUESTS-1:0][`NUM_THREADS-1:0][ADDR_WIDTH-1:0] in_io_req_addr,
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input wire [NUM_REQUESTS-1:0][`NUM_THREADS-1:0][WORD_WIDTH-1:0] in_io_req_data,
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input wire [NUM_REQUESTS-1:0][TAG_IN_WIDTH-1:0] in_io_req_tag,
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output wire [NUM_REQUESTS-1:0] in_io_req_ready,
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input wire [NUM_REQUESTS-1:0][`NUM_THREADS-1:0] io_req_valid_in,
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input wire [NUM_REQUESTS-1:0] io_req_rw_in,
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input wire [NUM_REQUESTS-1:0][`NUM_THREADS-1:0][WORD_SIZE-1:0] io_req_byteen_in,
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input wire [NUM_REQUESTS-1:0][`NUM_THREADS-1:0][ADDR_WIDTH-1:0] io_req_addr_in,
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input wire [NUM_REQUESTS-1:0][`NUM_THREADS-1:0][WORD_WIDTH-1:0] io_req_data_in,
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input wire [NUM_REQUESTS-1:0][TAG_IN_WIDTH-1:0] io_req_tag_in,
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output wire [NUM_REQUESTS-1:0] io_req_ready_in,
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// input response
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output wire [NUM_REQUESTS-1:0] in_io_rsp_valid,
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output wire [NUM_REQUESTS-1:0][WORD_WIDTH-1:0] in_io_rsp_data,
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output wire [NUM_REQUESTS-1:0][TAG_IN_WIDTH-1:0] in_io_rsp_tag,
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input wire [NUM_REQUESTS-1:0] in_io_rsp_ready,
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output wire [NUM_REQUESTS-1:0] io_rsp_valid_in,
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output wire [NUM_REQUESTS-1:0][WORD_WIDTH-1:0] io_rsp_data_in,
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output wire [NUM_REQUESTS-1:0][TAG_IN_WIDTH-1:0] io_rsp_tag_in,
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input wire [NUM_REQUESTS-1:0] io_rsp_ready_in,
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// output request
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output wire [`NUM_THREADS-1:0] out_io_req_valid,
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output wire out_io_req_rw,
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output wire [`NUM_THREADS-1:0][WORD_SIZE-1:0] out_io_req_byteen,
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output wire [`NUM_THREADS-1:0][ADDR_WIDTH-1:0] out_io_req_addr,
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output wire [`NUM_THREADS-1:0][WORD_WIDTH-1:0] out_io_req_data,
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output wire [TAG_OUT_WIDTH-1:0] out_io_req_tag,
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input wire out_io_req_ready,
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output wire [`NUM_THREADS-1:0] io_req_valid_out,
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output wire io_req_rw_out,
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output wire [`NUM_THREADS-1:0][WORD_SIZE-1:0] io_req_byteen_out,
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output wire [`NUM_THREADS-1:0][ADDR_WIDTH-1:0] io_req_addr_out,
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output wire [`NUM_THREADS-1:0][WORD_WIDTH-1:0] io_req_data_out,
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output wire [TAG_OUT_WIDTH-1:0] io_req_tag_out,
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input wire io_req_ready_out,
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// output response
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input wire out_io_rsp_valid,
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input wire [WORD_WIDTH-1:0] out_io_rsp_data,
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input wire [TAG_OUT_WIDTH-1:0] out_io_rsp_tag,
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output wire out_io_rsp_ready
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input wire io_rsp_valid_out,
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input wire [WORD_WIDTH-1:0] io_rsp_data_out,
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input wire [TAG_OUT_WIDTH-1:0] io_rsp_tag_out,
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output wire io_rsp_ready_out
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);
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if (NUM_REQUESTS == 1) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign out_io_req_valid = in_io_req_valid;
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assign out_io_req_rw = in_io_req_rw;
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assign out_io_req_byteen = in_io_req_byteen;
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assign out_io_req_addr = in_io_req_addr;
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assign out_io_req_data = in_io_req_data;
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assign out_io_req_tag = in_io_req_tag;
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assign in_io_req_ready = out_io_req_ready;
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assign io_req_valid_out = io_req_valid_in;
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assign io_req_rw_out = io_req_rw_in;
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assign io_req_byteen_out = io_req_byteen_in;
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assign io_req_addr_out = io_req_addr_in;
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assign io_req_data_out = io_req_data_in;
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assign io_req_tag_out = io_req_tag_in;
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assign io_req_ready_in = io_req_ready_out;
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assign in_io_rsp_valid = out_io_rsp_valid;
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assign in_io_rsp_data = out_io_rsp_data;
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assign in_io_rsp_tag = out_io_rsp_tag;
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assign out_io_rsp_ready = in_io_rsp_ready;
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assign io_rsp_valid_in = io_rsp_valid_out;
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assign io_rsp_data_in = io_rsp_data_out;
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assign io_rsp_tag_in = io_rsp_tag_out;
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assign io_rsp_ready_out = io_rsp_ready_in;
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end else begin
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@@ -68,7 +68,7 @@ module VX_io_arb #(
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wire [NUM_REQUESTS-1:0] valid_requests;
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for (genvar i = 0; i < NUM_REQUESTS; i++) begin
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assign valid_requests[i] = (| in_io_req_valid[i]);
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assign valid_requests[i] = (| io_req_valid_in[i]);
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end
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VX_rr_arbiter #(
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@@ -82,25 +82,25 @@ module VX_io_arb #(
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`UNUSED_PIN (grant_onehot)
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);
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assign out_io_req_valid = in_io_req_valid [bus_req_sel];
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assign out_io_req_rw = in_io_req_rw [bus_req_sel];
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assign out_io_req_byteen = in_io_req_byteen [bus_req_sel];
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assign out_io_req_addr = in_io_req_addr [bus_req_sel];
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assign out_io_req_data = in_io_req_data [bus_req_sel];
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assign out_io_req_tag = {in_io_req_tag [bus_req_sel], REQS_BITS'(bus_req_sel)};
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assign io_req_valid_out = io_req_valid_in [bus_req_sel];
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assign io_req_rw_out = io_req_rw_in [bus_req_sel];
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assign io_req_byteen_out = io_req_byteen_in [bus_req_sel];
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assign io_req_addr_out = io_req_addr_in [bus_req_sel];
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assign io_req_data_out = io_req_data_in [bus_req_sel];
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assign io_req_tag_out = {io_req_tag_in [bus_req_sel], REQS_BITS'(bus_req_sel)};
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for (genvar i = 0; i < NUM_REQUESTS; i++) begin
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assign in_io_req_ready[i] = out_io_req_ready && (bus_req_sel == REQS_BITS'(i));
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assign io_req_ready_in[i] = io_req_ready_out && (bus_req_sel == REQS_BITS'(i));
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end
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wire [REQS_BITS-1:0] bus_rsp_sel = out_io_rsp_tag[REQS_BITS-1:0];
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wire [REQS_BITS-1:0] bus_rsp_sel = io_rsp_tag_out[REQS_BITS-1:0];
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for (genvar i = 0; i < NUM_REQUESTS; i++) begin
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assign in_io_rsp_valid[i] = out_io_rsp_valid && (bus_rsp_sel == REQS_BITS'(i));
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assign in_io_rsp_data[i] = out_io_rsp_data;
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assign in_io_rsp_tag[i] = out_io_rsp_tag[REQS_BITS +: TAG_IN_WIDTH];
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assign io_rsp_valid_in[i] = io_rsp_valid_out && (bus_rsp_sel == REQS_BITS'(i));
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assign io_rsp_data_in[i] = io_rsp_data_out;
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assign io_rsp_tag_in[i] = io_rsp_tag_out[REQS_BITS +: TAG_IN_WIDTH];
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end
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assign out_io_rsp_ready = in_io_rsp_ready[bus_rsp_sel];
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assign io_rsp_ready_out = io_rsp_ready_in[bus_rsp_sel];
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end
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