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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count

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This commit is contained in:
Blaise Tine
2020-11-02 01:50:12 -08:00
parent 3fe31fc337
commit 5be1d85648
39 changed files with 1145 additions and 1322 deletions
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7
hw/rtl/VX_csr_unit.v
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@@ -13,7 +13,9 @@ module VX_csr_unit #(
VX_csr_io_rsp_if csr_io_rsp_if,
VX_csr_req_if csr_req_if,
VX_exu_to_cmt_if csr_commit_if
VX_exu_to_cmt_if csr_commit_if,
input wire busy
);
VX_csr_req_if csr_pipe_req_if();
VX_exu_to_cmt_if csr_pipe_rsp_if();
@@ -53,7 +55,8 @@ module VX_csr_unit #(
.write_enable (csr_we_s1),
.write_addr (csr_addr_s1),
.write_wid (csr_pipe_rsp_if.wid),
.write_data (csr_updated_data_s1[`CSR_WIDTH-1:0])
.write_data (csr_updated_data_s1[`CSR_WIDTH-1:0]),
.busy (busy)
);
wire csr_hazard = (csr_addr_s1 == csr_pipe_req_if.csr_addr)