merging changes from OPAE branch making this branch
This commit is contained in:
Blaise Tine
100
old_rtl/simulate/VX_define.h
Normal file
100
old_rtl/simulate/VX_define.h
Normal file
@@ -0,0 +1,100 @@
|
||||
#define NT 4
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#define NT_M1 (NT-1)
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#define NW 8
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||||
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#define CACHE_NUM_BANKS 8
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||||
#define CACHE_WORDS_PER_BLOCK 4
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||||
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||||
#define R_INST 51
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#define L_INST 3
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#define ALU_INST 19
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#define S_INST 35
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#define B_INST 99
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#define LUI_INST 55
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#define AUIPC_INST 23
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#define JAL_INST 111
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#define JALR_INST 103
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#define SYS_INST 115
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#define WB_ALU 1
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#define WB_MEM 2
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#define WB_JAL 3
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#define NO_WB 0
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#define RS2_IMMED 1
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#define RS2_REG 0
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#define NO_MEM_READ 7
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#define LB_MEM_READ 0
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#define LH_MEM_READ 1
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#define LW_MEM_READ 2
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#define LBU_MEM_READ 4
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#define LHU_MEM_READ 5
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#define NO_MEM_WRITE 7
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#define SB_MEM_WRITE 0
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#define SH_MEM_WRITE 1
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#define SW_MEM_WRITE 2
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||||
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||||
#define NO_BRANCH 0
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#define BEQ 1
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#define BNE 2
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#define BLT 3
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#define BGT 4
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#define BLTU 5
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#define BGTU 6
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#define NO_ALU 15
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#define ADD 0
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#define SUB 1
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#define SLLA 2
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#define SLT 3
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#define SLTU 4
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#define XOR 5
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#define SRL 6
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#define SRA 7
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#define OR 8
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#define AND 9
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#define SUBU 10
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#define LUI_ALU 11
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#define AUIPC_ALU 12
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#define CSR_ALU_RW 13
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#define CSR_ALU_RS 14
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#define CSR_ALU_RC 15
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// WRITEBACK
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#define WB_ALU 1
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#define WB_MEM 2
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#define WB_JAL 3
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#define NO_WB 0
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||||
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// JAL
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#define JUMP 1
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#define NO_JUMP 0
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// STALLS
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#define STALL 1
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#define NO_STALL 0
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#define TAKEN 1
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||||
#define NOT_TAKEN 0
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||||
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#define ZERO_REG 0
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// COLORS
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#define GREEN "\033[32m"
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#define RED "\033[31m"
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#define DEFAULT "\033[39m"
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245
old_rtl/simulate/ram.h
Normal file
245
old_rtl/simulate/ram.h
Normal file
@@ -0,0 +1,245 @@
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||||
#ifndef __RAM__
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#define __RAM__
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// #include "string.h"
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#include <stdio.h>
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#include <stdint.h>
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// #include <cstdint>
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// #define NULL 0
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class RAM;
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uint32_t hti(char);
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uint32_t hToI(char *, uint32_t);
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void loadHexImpl(char *,RAM*);
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class RAM{
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public:
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uint8_t* mem[1 << 12];
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RAM(){
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for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL;
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}
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~RAM(){
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for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i];
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}
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void clear(){
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for(uint32_t i = 0;i < (1 << 12);i++)
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{
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||||
if(mem[i])
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||||
{
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delete mem[i];
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mem[i] = NULL;
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||||
}
|
||||
}
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||||
}
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||||
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uint8_t* get(uint32_t address){
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||||
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||||
if(mem[address >> 20] == NULL) {
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uint8_t* ptr = new uint8_t[1024*1024];
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for(uint32_t i = 0;i < 1024*1024;i+=4) {
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ptr[i + 0] = 0x00;
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ptr[i + 1] = 0x00;
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ptr[i + 2] = 0x00;
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ptr[i + 3] = 0x00;
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}
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mem[address >> 20] = ptr;
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}
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return &mem[address >> 20][address & 0xFFFFF];
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}
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void read(uint32_t address,uint32_t length, uint8_t *data){
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for(unsigned i = 0;i < length;i++){
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data[i] = (*this)[address + i];
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}
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}
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void write(uint32_t address,uint32_t length, uint8_t *data){
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for(unsigned i = 0;i < length;i++){
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(*this)[address + i] = data[i];
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}
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}
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void getBlock(uint32_t address, uint8_t *data)
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{
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uint32_t block_number = address & 0xffffff00; // To zero out block offset
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uint32_t bytes_num = 256;
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this->read(block_number, bytes_num, data);
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}
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void getWord(uint32_t address, uint32_t * data)
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{
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data[0] = 0;
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uint8_t first = *get(address + 0);
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uint8_t second = *get(address + 1);
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uint8_t third = *get(address + 2);
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uint8_t fourth = *get(address + 3);
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// uint8_t hi = (uint8_t) *get(address + 0);
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// std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << hi << "\n";
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// hi = (uint8_t) *get(address + 1);
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// std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << hi << "\n";
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// hi = (uint8_t) *get(address + 2);
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// std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << hi << "\n";
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// hi = (uint8_t) *get(address + 3);
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// std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << hi << "\n";
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||||
data[0] = (data[0] << 0) | fourth;
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data[0] = (data[0] << 8) | third;
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data[0] = (data[0] << 8) | second;
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data[0] = (data[0] << 8) | first;
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}
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void writeWord(uint32_t address, uint32_t * data)
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{
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uint32_t data_to_write = *data;
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uint32_t byte_mask = 0xFF;
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for (int i = 0; i < 4; i++)
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{
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// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
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// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
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// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
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(*this)[address + i] = data_to_write & byte_mask;
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data_to_write = data_to_write >> 8;
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}
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}
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void writeHalf(uint32_t address, uint32_t * data)
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{
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uint32_t data_to_write = *data;
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uint32_t byte_mask = 0xFF;
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||||
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for (int i = 0; i < 2; i++)
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||||
{
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// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
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// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
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// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
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(*this)[address + i] = data_to_write & byte_mask;
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data_to_write = data_to_write >> 8;
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}
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}
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void writeByte(uint32_t address, uint32_t * data)
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{
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uint32_t data_to_write = *data;
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uint32_t byte_mask = 0xFF;
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(*this)[address] = data_to_write & byte_mask;
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data_to_write = data_to_write >> 8;
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}
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uint8_t& operator [](uint32_t address) {
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return *get(address);
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}
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};
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// MEMORY UTILS
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uint32_t hti(char c) {
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if (c >= 'A' && c <= 'F')
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return c - 'A' + 10;
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if (c >= 'a' && c <= 'f')
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return c - 'a' + 10;
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return c - '0';
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}
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uint32_t hToI(char *c, uint32_t size) {
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uint32_t value = 0;
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for (uint32_t i = 0; i < size; i++) {
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value += hti(c[i]) << ((size - i - 1) * 4);
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}
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return value;
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}
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void loadHexImpl(const char *path, RAM* mem) {
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mem->clear();
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FILE *fp = fopen(path, "r");
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if(fp == 0){
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printf("Path not found %s\n", path);
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return;
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// std::cout << path << " not found" << std::endl;
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}
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//Preload 0x0 <-> 0x80000000 jumps
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((uint32_t*)mem->get(0))[1] = 0xf1401073;
|
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((uint32_t*)mem->get(0))[2] = 0x30101073;
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((uint32_t*)mem->get(0))[3] = 0x800000b7;
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((uint32_t*)mem->get(0))[4] = 0x000080e7;
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((uint32_t*)mem->get(0x80000000))[0] = 0x00000097;
|
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|
||||
((uint32_t*)mem->get(0xb0000000))[0] = 0x01C02023;
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// F00FFF10
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((uint32_t*)mem->get(0xf00fff10))[0] = 0x12345678;
|
||||
|
||||
|
||||
|
||||
|
||||
fseek(fp, 0, SEEK_END);
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uint32_t size = ftell(fp);
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fseek(fp, 0, SEEK_SET);
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char* content = new char[size];
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fread(content, 1, size, fp);
|
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|
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int offset = 0;
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char* line = content;
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// std::cout << "WHTA\n";
|
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while (1) {
|
||||
if (line[0] == ':') {
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uint32_t byteCount = hToI(line + 1, 2);
|
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uint32_t nextAddr = hToI(line + 3, 4) + offset;
|
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uint32_t key = hToI(line + 7, 2);
|
||||
switch (key) {
|
||||
case 0:
|
||||
for (uint32_t i = 0; i < byteCount; i++) {
|
||||
|
||||
unsigned add = nextAddr + i;
|
||||
|
||||
*(mem->get(add)) = hToI(line + 9 + i * 2, 2);
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
// cout << offset << endl;
|
||||
offset = hToI(line + 9, 4) << 4;
|
||||
break;
|
||||
case 4:
|
||||
// cout << offset << endl;
|
||||
offset = hToI(line + 9, 4) << 16;
|
||||
break;
|
||||
default:
|
||||
// cout << "??? " << key << endl;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
while (*line != '\n' && size != 0) {
|
||||
line++;
|
||||
size--;
|
||||
}
|
||||
if (size <= 1)
|
||||
break;
|
||||
line++;
|
||||
size--;
|
||||
}
|
||||
|
||||
if (content) delete[] content;
|
||||
}
|
||||
|
||||
#endif
|
||||
1
old_rtl/simulate/tb_debug.h
Normal file
1
old_rtl/simulate/tb_debug.h
Normal file
@@ -0,0 +1 @@
|
||||
#define VCD_OFF
|
||||
105
old_rtl/simulate/test_bench.cpp
Normal file
105
old_rtl/simulate/test_bench.cpp
Normal file
@@ -0,0 +1,105 @@
|
||||
#include "test_bench.h"
|
||||
|
||||
#define NUM_TESTS 46
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
|
||||
// Verilated::debug(1);
|
||||
|
||||
Verilated::commandArgs(argc, argv);
|
||||
|
||||
Verilated::traceEverOn(true);
|
||||
|
||||
|
||||
#define ALL_TESTS
|
||||
#ifdef ALL_TESTS
|
||||
bool passed = true;
|
||||
std::string tests[NUM_TESTS] = {
|
||||
"../../emulator/riscv_tests/rv32ui-p-add.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-addi.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-and.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-andi.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-auipc.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-beq.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-bge.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-blt.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-bltu.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-bne.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-jal.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-jalr.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-lb.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-lbu.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-lh.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-lhu.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-lui.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-lw.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-or.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-ori.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-sb.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-sh.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-simple.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-sll.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-slli.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-slt.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-slti.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-sltu.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-sra.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-srai.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-srl.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-srli.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-sub.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-sw.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-xor.hex",
|
||||
"../../emulator/riscv_tests/rv32ui-p-xori.hex",
|
||||
"../../emulator/riscv_tests/rv32um-p-div.hex",
|
||||
"../../emulator/riscv_tests/rv32um-p-divu.hex",
|
||||
"../../emulator/riscv_tests/rv32um-p-mul.hex",
|
||||
"../../emulator/riscv_tests/rv32um-p-mulh.hex",
|
||||
"../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
|
||||
"../../emulator/riscv_tests/rv32um-p-mulhu.hex",
|
||||
"../../emulator/riscv_tests/rv32um-p-rem.hex",
|
||||
"../../emulator/riscv_tests/rv32um-p-remu.hex"
|
||||
};
|
||||
|
||||
for (std::string s : tests) {
|
||||
Vortex v;
|
||||
|
||||
std::cerr << s << std::endl;
|
||||
|
||||
bool curr = v.simulate(s);
|
||||
if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
|
||||
if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl;
|
||||
passed = passed && curr;
|
||||
}
|
||||
|
||||
if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
|
||||
if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
|
||||
|
||||
return !passed;
|
||||
|
||||
#else
|
||||
|
||||
char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
|
||||
Vortex v;
|
||||
const char *testing;
|
||||
|
||||
if (argc >= 2) {
|
||||
testing = argv[1];
|
||||
} else {
|
||||
testing = "../../kernel/vortex_test.hex";
|
||||
}
|
||||
|
||||
std::cerr << testing << std::endl;
|
||||
|
||||
|
||||
bool curr = v.simulate(testing);
|
||||
if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
|
||||
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
|
||||
|
||||
return !curr;
|
||||
|
||||
#endif
|
||||
}
|
||||
433
old_rtl/simulate/test_bench.h
Normal file
433
old_rtl/simulate/test_bench.h
Normal file
@@ -0,0 +1,433 @@
|
||||
// C++ libraries
|
||||
#include <utility>
|
||||
#include <iostream>
|
||||
#include <map>
|
||||
#include <iterator>
|
||||
#include <iomanip>
|
||||
#include <fstream>
|
||||
#include <unistd.h>
|
||||
#include <vector>
|
||||
#include <math.h>
|
||||
#include <algorithm>
|
||||
|
||||
#include "VX_define.h"
|
||||
#include "ram.h"
|
||||
#include "VVortex.h"
|
||||
#include "verilated.h"
|
||||
|
||||
#include "tb_debug.h"
|
||||
|
||||
#ifdef VCD_OUTPUT
|
||||
#include <verilated_vcd_c.h>
|
||||
#endif
|
||||
|
||||
unsigned long time_stamp = 0;
|
||||
|
||||
double sc_time_stamp()
|
||||
{
|
||||
return time_stamp / 1000.0;
|
||||
}
|
||||
|
||||
class Vortex
|
||||
{
|
||||
public:
|
||||
Vortex();
|
||||
~Vortex();
|
||||
bool simulate(std::string);
|
||||
private:
|
||||
void ProcessFile(void);
|
||||
void print_stats(bool = true);
|
||||
bool ibus_driver();
|
||||
bool dbus_driver();
|
||||
void io_handler();
|
||||
|
||||
RAM ram;
|
||||
|
||||
VVortex * vortex;
|
||||
|
||||
unsigned start_pc;
|
||||
bool refill_d;
|
||||
unsigned refill_addr_d;
|
||||
bool refill_i;
|
||||
unsigned refill_addr_i;
|
||||
long int curr_cycle;
|
||||
bool stop;
|
||||
bool unit_test;
|
||||
std::string instruction_file_name;
|
||||
std::ofstream results;
|
||||
int stats_static_inst;
|
||||
int stats_dynamic_inst;
|
||||
int stats_total_cycles;
|
||||
int stats_fwd_stalls;
|
||||
int stats_branch_stalls;
|
||||
int debug_state;
|
||||
int ibus_state;
|
||||
int dbus_state;
|
||||
int debug_return;
|
||||
int debug_wait_num;
|
||||
int debug_inst_num;
|
||||
int debug_end_wait;
|
||||
int debug_debugAddr;
|
||||
double stats_sim_time;
|
||||
#ifdef VCD_OUTPUT
|
||||
VerilatedVcdC *m_trace;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
|
||||
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
|
||||
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
|
||||
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
|
||||
{
|
||||
this->vortex = new VVortex;
|
||||
#ifdef VCD_OUTPUT
|
||||
this->m_trace = new VerilatedVcdC;
|
||||
this->vortex->trace(m_trace, 99);
|
||||
this->m_trace->open("trace.vcd");
|
||||
#endif
|
||||
this->results.open("../results.txt");
|
||||
}
|
||||
|
||||
Vortex::~Vortex()
|
||||
{
|
||||
#ifdef VCD_OUTPUT
|
||||
m_trace->close();
|
||||
#endif
|
||||
this->results.close();
|
||||
delete this->vortex;
|
||||
}
|
||||
|
||||
|
||||
void Vortex::ProcessFile(void)
|
||||
{
|
||||
loadHexImpl(this->instruction_file_name.c_str(), &this->ram);
|
||||
}
|
||||
|
||||
void Vortex::print_stats(bool cycle_test)
|
||||
{
|
||||
|
||||
if (cycle_test)
|
||||
{
|
||||
this->results << std::left;
|
||||
// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
|
||||
this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
|
||||
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
|
||||
this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
|
||||
this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
|
||||
this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
|
||||
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
|
||||
}
|
||||
else
|
||||
{
|
||||
this->results << std::left;
|
||||
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
|
||||
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
|
||||
}
|
||||
|
||||
|
||||
uint32_t status;
|
||||
ram.getWord(0, &status);
|
||||
|
||||
if (this->unit_test)
|
||||
{
|
||||
if (status == 1)
|
||||
{
|
||||
this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
|
||||
} else
|
||||
{
|
||||
this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
|
||||
}
|
||||
|
||||
this->stats_static_inst = 0;
|
||||
this->stats_dynamic_inst = -1;
|
||||
this->stats_total_cycles = 0;
|
||||
this->stats_fwd_stalls = 0;
|
||||
this->stats_branch_stalls = 0;
|
||||
|
||||
}
|
||||
|
||||
bool Vortex::ibus_driver()
|
||||
{
|
||||
|
||||
vortex->i_m_ready_i = false;
|
||||
|
||||
{
|
||||
|
||||
// int dcache_num_words_per_block
|
||||
|
||||
if (refill_i)
|
||||
{
|
||||
refill_i = false;
|
||||
vortex->i_m_ready_i = true;
|
||||
|
||||
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++)
|
||||
{
|
||||
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++)
|
||||
{
|
||||
unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank;
|
||||
unsigned curr_addr = refill_addr_i + (4*curr_index);
|
||||
|
||||
unsigned curr_value;
|
||||
ram.getWord(curr_addr, &curr_value);
|
||||
|
||||
vortex->i_m_readdata_i[curr_bank][curr_word] = curr_value;
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (vortex->o_m_valid_i)
|
||||
{
|
||||
|
||||
if (vortex->o_m_read_or_write_i)
|
||||
{
|
||||
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
|
||||
unsigned base_addr = vortex->o_m_evict_addr_i;
|
||||
|
||||
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++)
|
||||
{
|
||||
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++)
|
||||
{
|
||||
unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank;
|
||||
unsigned curr_addr = base_addr + (4*curr_index);
|
||||
|
||||
unsigned curr_value = vortex->o_m_writedata_i[curr_bank][curr_word];
|
||||
|
||||
ram.writeWord( curr_addr, &curr_value);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Respond next cycle
|
||||
refill_i = true;
|
||||
refill_addr_i = vortex->o_m_read_addr_i;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
return false;
|
||||
|
||||
}
|
||||
|
||||
void Vortex::io_handler()
|
||||
{
|
||||
if (vortex->io_valid)
|
||||
{
|
||||
uint32_t data_write = (uint32_t) vortex->io_data;
|
||||
|
||||
char c = (char) data_write;
|
||||
std::cerr << c;
|
||||
// std::cout << c;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
bool Vortex::dbus_driver()
|
||||
{
|
||||
|
||||
vortex->i_m_ready_d = false;
|
||||
|
||||
{
|
||||
|
||||
// int dcache_num_words_per_block
|
||||
|
||||
if (refill_d)
|
||||
{
|
||||
refill_d = false;
|
||||
vortex->i_m_ready_d = true;
|
||||
|
||||
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++)
|
||||
{
|
||||
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++)
|
||||
{
|
||||
unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank;
|
||||
unsigned curr_addr = refill_addr_d + (4*curr_index);
|
||||
|
||||
unsigned curr_value;
|
||||
ram.getWord(curr_addr, &curr_value);
|
||||
|
||||
vortex->i_m_readdata_d[curr_bank][curr_word] = curr_value;
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (vortex->o_m_valid_d)
|
||||
{
|
||||
|
||||
if (vortex->o_m_read_or_write_d)
|
||||
{
|
||||
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
|
||||
unsigned base_addr = vortex->o_m_evict_addr_d;
|
||||
|
||||
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++)
|
||||
{
|
||||
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++)
|
||||
{
|
||||
unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank;
|
||||
unsigned curr_addr = base_addr + (4*curr_index);
|
||||
|
||||
unsigned curr_value = vortex->o_m_writedata_d[curr_bank][curr_word];
|
||||
|
||||
ram.writeWord( curr_addr, &curr_value);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Respond next cycle
|
||||
refill_d = true;
|
||||
refill_addr_d = vortex->o_m_read_addr_d;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
|
||||
bool Vortex::simulate(std::string file_to_simulate)
|
||||
{
|
||||
|
||||
this->instruction_file_name = file_to_simulate;
|
||||
// this->results << "\n****************\t" << file_to_simulate << "\t****************\n";
|
||||
|
||||
this->ProcessFile();
|
||||
|
||||
// auto start_time = std::chrono::high_resolution_clock::now();
|
||||
|
||||
|
||||
static bool stop = false;
|
||||
static int counter = 0;
|
||||
counter = 0;
|
||||
stop = false;
|
||||
|
||||
// auto start_time = clock();
|
||||
|
||||
|
||||
// vortex->reset = 1;
|
||||
|
||||
|
||||
// vortex->reset = 0;
|
||||
|
||||
unsigned curr_inst;
|
||||
unsigned new_PC;
|
||||
|
||||
// while (this->stop && (!(stop && (counter > 5))))
|
||||
// {
|
||||
|
||||
// // std::cout << "************* Cycle: " << cycle << "\n";
|
||||
// bool istop = ibus_driver();
|
||||
// bool dstop = !dbus_driver();
|
||||
|
||||
// vortex->clk = 1;
|
||||
// vortex->eval();
|
||||
|
||||
|
||||
|
||||
// vortex->clk = 0;
|
||||
// vortex->eval();
|
||||
|
||||
|
||||
// stop = istop && dstop;
|
||||
|
||||
// if (stop)
|
||||
// {
|
||||
// counter++;
|
||||
// } else
|
||||
// {
|
||||
// counter = 0;
|
||||
// }
|
||||
|
||||
// cycle++;
|
||||
// }
|
||||
|
||||
bool istop;
|
||||
bool dstop;
|
||||
bool cont = false;
|
||||
// for (int i = 0; i < 500; i++)
|
||||
|
||||
vortex->reset = 1;
|
||||
vortex->clk = 0;
|
||||
vortex->eval();
|
||||
// m_trace->dump(10);
|
||||
vortex->reset = 1;
|
||||
vortex->clk = 1;
|
||||
vortex->eval();
|
||||
// m_trace->dump(11);
|
||||
vortex->reset = 0;
|
||||
vortex->clk = 0;
|
||||
|
||||
// unsigned cycles;
|
||||
counter = 0;
|
||||
this->stats_total_cycles = 12;
|
||||
while (this->stop && ((counter < 5)))
|
||||
// while (this->stats_total_cycles < 10)
|
||||
{
|
||||
|
||||
// printf("-------------------------\n");
|
||||
// std::cout << "Counter: " << counter << "\n";
|
||||
// if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
|
||||
// dstop = !dbus_driver();
|
||||
#ifdef VCD_OUTPUT
|
||||
m_trace->dump(2*this->stats_total_cycles);
|
||||
#endif
|
||||
vortex->clk = 1;
|
||||
vortex->eval();
|
||||
istop = ibus_driver();
|
||||
dstop = !dbus_driver();
|
||||
io_handler();
|
||||
|
||||
#ifdef VCD_OUTPUT
|
||||
m_trace->dump((2*this->stats_total_cycles)+1);
|
||||
#endif
|
||||
vortex->clk = 0;
|
||||
vortex->eval();
|
||||
// stop = istop && dstop;
|
||||
stop = vortex->out_ebreak;
|
||||
|
||||
if (stop || cont)
|
||||
// if (istop)
|
||||
{
|
||||
cont = true;
|
||||
counter++;
|
||||
} else
|
||||
{
|
||||
counter = 0;
|
||||
}
|
||||
|
||||
++time_stamp;
|
||||
++stats_total_cycles;
|
||||
}
|
||||
|
||||
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
|
||||
|
||||
int status = (unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf;
|
||||
|
||||
// std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";
|
||||
|
||||
// std::cout << "Something: " << result << '\n';
|
||||
|
||||
// uint32_t status;
|
||||
// ram.getWord(0, &status);
|
||||
|
||||
this->print_stats();
|
||||
|
||||
|
||||
|
||||
return (status == 1);
|
||||
// return (1 == 1);
|
||||
}
|
||||
Reference in New Issue
Block a user