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rtl multicore fix

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This commit is contained in:
Blaise Tine
2020-05-06 13:33:16 -04:00
parent 330bbc4f56
commit 59cc0d5be9
5 changed files with 15 additions and 18 deletions
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14
hw/simulate/simulator.cpp
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@@ -158,17 +158,15 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
// submit snoop requests for the needed blocks
vortex_->snp_req_addr = aligned_addr_start;
vortex_->snp_req_valid = false;
vortex_->snp_req_valid = true;
for (;;) {
this->step();
if (vortex_->snp_req_valid) {
vortex_->snp_req_valid = false;
if (vortex_->snp_req_addr >= aligned_addr_end)
break;
if (vortex_->snp_req_valid && vortex_->snp_req_ready) {
vortex_->snp_req_addr += 1;
}
if (vortex_->snp_req_ready) {
vortex_->snp_req_valid = true;
if (vortex_->snp_req_addr >= aligned_addr_end) {
vortex_->snp_req_valid = false;
break;
}
}
}
this->wait(PIPELINE_FLUSH_LATENCY);

2
hw/simulate/simulator.h
View File

@@ -18,7 +18,7 @@
#define DRAM_LATENCY 100
#define DRAM_RQ_SIZE 16
#define DRAM_STALLS_MODULO 16
#define PIPELINE_FLUSH_LATENCY 300
#define PIPELINE_FLUSH_LATENCY 1000
typedef struct {
int cycles_left;