merge update

2021-10-15 19:58:13 -07:00
parent e380ded5e1
commit 58a2140b92
31 changed files with 169 additions and 98 deletions
--- a/hw/rtl/interfaces/VX_tex_csr_if.sv
+++ b/hw/rtl/interfaces/VX_tex_csr_if.sv
@@ -7,7 +7,19 @@ interface VX_tex_csr_if ();

    wire                      write_enable; 
    wire [`CSR_ADDR_BITS-1:0] write_addr;
-    wire [31:0]               write_data;   
+    wire [31:0]               write_data;  
+
+    modport master (
+        output write_enable,
+        output write_addr,
+        output write_data
+    );
+
+    modport slave (
+        input write_enable,
+        input write_addr,
+        input write_data
+    );

 endinterface