merge update

2021-10-15 19:58:13 -07:00
parent e380ded5e1
commit 58a2140b92
31 changed files with 169 additions and 98 deletions
--- a/hw/rtl/VX_csr_unit.sv
+++ b/hw/rtl/VX_csr_unit.sv
@@ -21,7 +21,7 @@ module VX_csr_unit #(
    input wire[`NUM_WARPS-1:0]  fpu_pending,
 `endif
 `ifdef EXT_TEX_ENABLE
-    VX_tex_csr_if.slave         tex_csr_if,
+    VX_tex_csr_if.master        tex_csr_if,
 `endif

    output wire[`NUM_WARPS-1:0] pending,
@@ -49,6 +49,7 @@ module VX_csr_unit #(
        .fetch_to_csr_if(fetch_to_csr_if),
    `ifdef EXT_F_ENABLE
        .fpu_to_csr_if  (fpu_to_csr_if), 
+    `endif
    `ifdef EXT_TEX_ENABLE
        .tex_csr_if     (tex_csr_if),
    `endif