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RTL code refactoring

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Blaise Tine
2020-04-20 06:59:13 -04:00
parent 07135263f5
commit 58850a2fe8
6 changed files with 22 additions and 23 deletions
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7
hw/rtl/interfaces/VX_gpu_dcache_req_if.v
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@@ -13,14 +13,13 @@ interface VX_gpu_dcache_req_if #(
wire [NUM_REQUESTS-1:0][2:0] core_req_mem_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][31:0] core_req_writedata;
wire core_req_ready;
// Core request Meta data
wire [4:0] core_req_rd;
wire [NUM_REQUESTS-1:0][1:0] core_req_wb;
wire [`NW_BITS-1:0] core_req_warp_num;
wire [31:0] core_req_pc;
wire core_no_wb_slot;
wire [31:0] core_req_pc;
endinterface

5
hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
View File

@@ -15,11 +15,10 @@ interface VX_gpu_dcache_rsp_if #(
`IGNORE_WARNINGS_END
wire [NUM_REQUESTS-1:0][31:0] core_wb_pc;
wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata;
wire core_no_wb_slot;
// Core response meta data
wire [`NW_BITS-1:0] core_wb_warp_num;
wire core_req_ready;
wire [`NW_BITS-1:0] core_wb_warp_num;
endinterface