pipeline refactoring
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@@ -17,43 +17,29 @@ module VX_execute #(
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VX_cache_core_req_if dcache_req_if,
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VX_cache_core_rsp_if dcache_rsp_if,
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// inputs
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VX_execute_if execute_if,
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VX_wb_if writeback_if,
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// perf
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VX_perf_cntrs_if perf_cntrs_if,
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// inputs
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VX_alu_req_if alu_req_if,
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VX_branch_req_if branch_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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VX_gpu_req_if gpu_req_if,
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// outputs
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VX_branch_rsp_if branch_rsp_if,
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VX_branch_ctl_if branch_ctl_if,
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VX_warp_ctl_if warp_ctl_if,
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VX_wb_if alu_wb_if,
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VX_wb_if branch_wb_if,
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VX_wb_if lsu_wb_if,
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VX_wb_if csr_wb_if,
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VX_wb_if mul_wb_if,
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input wire notify_commit,
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VX_commit_if alu_commit_if,
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VX_commit_if branch_commit_if,
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VX_commit_if lsu_commit_if,
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VX_commit_if csr_commit_if,
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VX_commit_if mul_commit_if,
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VX_commit_if gpu_commit_if,
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output wire ebreak
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);
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VX_alu_req_if alu_req_if();
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VX_branch_req_if branch_req_if();
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VX_csr_req_if csr_req_if();
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VX_lsu_req_if lsu_req_if();
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VX_mul_req_if mul_req_if();
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VX_gpu_req_if gpu_req_if();
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VX_gpr_stage #(
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.CORE_ID(CORE_ID)
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) gpr_stage (
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.clk (clk),
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.reset (reset),
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.writeback_if (writeback_if),
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.execute_if (execute_if),
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.alu_req_if (alu_req_if),
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.branch_req_if (branch_req_if),
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.lsu_req_if (lsu_req_if),
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.csr_req_if (csr_req_if),
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.mul_req_if (mul_req_if),
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.gpu_req_if (gpu_req_if)
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);
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VX_alu_unit #(
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.CORE_ID(CORE_ID)
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@@ -61,7 +47,7 @@ module VX_execute #(
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.clk (clk),
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.reset (reset),
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.alu_req_if (alu_req_if),
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.alu_wb_if (alu_wb_if)
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.alu_commit_if (alu_commit_if)
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);
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VX_branch_unit #(
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@@ -70,8 +56,8 @@ module VX_execute #(
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.clk (clk),
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.reset (reset),
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.branch_req_if (branch_req_if),
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.branch_rsp_if (branch_rsp_if),
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.branch_wb_if (branch_wb_if)
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.branch_ctl_if (branch_ctl_if),
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.branch_commit_if(branch_commit_if)
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);
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VX_lsu_unit #(
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@@ -83,19 +69,19 @@ module VX_execute #(
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.dcache_req_if (dcache_req_if),
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.dcache_rsp_if (dcache_rsp_if),
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.lsu_req_if (lsu_req_if),
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.lsu_wb_if (lsu_wb_if)
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.lsu_commit_if (lsu_commit_if)
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);
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VX_csr_pipe #(
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.CORE_ID(CORE_ID)
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) csr_pipe (
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.clk (clk),
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.reset (reset),
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.csr_req_if (csr_req_if),
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.csr_io_req_if (csr_io_req_if),
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.csr_wb_if (csr_wb_if),
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.reset (reset),
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.perf_cntrs_if (perf_cntrs_if),
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.csr_io_req_if (csr_io_req_if),
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.csr_io_rsp_if (csr_io_rsp_if),
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.notify_commit (notify_commit)
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.csr_req_if (csr_req_if),
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.csr_commit_if (csr_commit_if)
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);
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VX_mul_unit #(
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@@ -104,14 +90,15 @@ module VX_execute #(
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.clk (clk),
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.reset (reset),
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.mul_req_if (mul_req_if),
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.mul_wb_if (mul_wb_if)
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.mul_commit_if (mul_commit_if)
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);
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VX_gpu_unit #(
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.CORE_ID(CORE_ID)
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) gpu_unit (
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.gpu_req_if (gpu_req_if),
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.warp_ctl_if (warp_ctl_if)
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.warp_ctl_if (warp_ctl_if),
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.gpu_commit_if (gpu_commit_if)
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);
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assign ebreak = (| branch_req_if.valid) && (branch_req_if.br_op == `BR_EBREAK || branch_req_if.br_op == `BR_ECALL);
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