pipeline refactoring
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@@ -10,8 +10,8 @@ module VX_branch_unit #(
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VX_branch_req_if branch_req_if,
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// Outputs
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VX_branch_rsp_if branch_rsp_if,
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VX_wb_if branch_wb_if
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VX_branch_ctl_if branch_ctl_if,
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VX_commit_if branch_commit_if
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);
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wire [`NT_BITS-1:0] br_result_index;
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@@ -19,7 +19,7 @@ module VX_branch_unit #(
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VX_priority_encoder #(
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.N(`NUM_THREADS)
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) choose_alu_result (
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.data_in (alu_req_if.valid),
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.data_in (branch_req_if.valid),
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.data_out (br_result_index),
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`UNUSED_PIN (valid_out)
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);
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@@ -53,7 +53,7 @@ module VX_branch_unit #(
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wire [31:0] base_addr = (br_op == `BR_JALR) ? rs1_data : branch_req_if.curr_PC;
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wire [31:0] br_dest = $signed(base_addr) + $signed(branch_req_if.offset);
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wire stall = (~branch_wb_if.ready && (| branch_wb_if.valid));
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wire stall = (~branch_commit_if.ready && (| branch_commit_if.valid));
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VX_generic_register #(
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.N(1 + `NW_BITS + 1 + 32)
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@@ -63,7 +63,7 @@ module VX_branch_unit #(
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.stall (stall),
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.flush (0),
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.in ({in_valid, branch_req_if.warp_num, br_taken, br_dest}),
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.out ({branch_rsp_if.valid, branch_rsp_if.warp_num, branch_rsp_if.taken, branch_rsp_if.dest})
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.out ({branch_ctl_if.valid, branch_ctl_if.warp_num, branch_ctl_if.taken, branch_ctl_if.dest})
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);
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VX_generic_register #(
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@@ -74,7 +74,7 @@ module VX_branch_unit #(
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.stall (stall),
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.flush (0),
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.in ({branch_req_if.valid, branch_req_if.warp_num, branch_req_if.curr_PC, branch_req_if.rd, branch_req_if.wb, {`NUM_THREADS{branch_req_if.next_PC}}}),
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.out ({branch_wb_if.valid, branch_wb_if.warp_num, branch_wb_if.curr_PC, branch_wb_if.rd, branch_wb_if.wb, branch_wb_if.data})
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.out ({branch_commit_if.valid, branch_commit_if.warp_num, branch_commit_if.curr_PC, branch_commit_if.rd, branch_commit_if.wb, branch_commit_if.data})
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);
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assign branch_req_if.ready = ~stall;
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