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generic_register reset network optimization

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Blaise Tine
2020-11-29 18:41:36 -08:00
parent def6a35693
commit 5758ef9ebf
21 changed files with 84 additions and 48 deletions
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4
hw/rtl/libs/VX_cam_buffer.v
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@@ -54,7 +54,9 @@ module VX_cam_buffer #(
end else begin
for (integer i = 0; i < CPORTS; i++) begin
if (release_slot[i]) begin
assert(0 == free_slots[release_addr[i]]) else $error("%t: releasing invalid slot at port %d", $time, release_addr[i]);
assert(0 == free_slots[release_addr[i]]) else begin
$display("%t: releasing invalid slot at port %d", $time, release_addr[i]);
end
end
end
free_slots <= free_slots_n;

26
hw/rtl/libs/VX_generic_register.v
View File

@@ -1,7 +1,8 @@
`include "VX_platform.vh"
module VX_generic_register #(
parameter N = 1,
parameter N = 1,
parameter R = N,
parameter PASSTHRU = 0
) (
input wire clk,
@@ -17,13 +18,24 @@ module VX_generic_register #(
`UNUSED_VAR (stall)
assign out = flush ? N'(0) : in;
end else begin
reg [(N-1):0] value;
reg [N-1:0] value;
always @(posedge clk) begin
if (reset || flush) begin
value <= N'(0);
end else if (~stall) begin
value <= in;
if (R != 0) begin
always @(posedge clk) begin
if (~stall) begin
value <= in;
end
if (reset || flush) begin
value[N-1:N-R] <= R'(0);
end
end
end else begin
`UNUSED_VAR (reset)
`UNUSED_VAR (flush)
always @(posedge clk) begin
if (~stall) begin
value <= in;
end
end
end