synthesis optimizations

2021-06-17 16:43:43 -07:00
parent 1e677c8e5e
commit 57143f5889
16 changed files with 173 additions and 229 deletions
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -475,8 +475,7 @@ module VX_bank #(
    end

    VX_skid_buffer #(
-        .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
-        .USE_FASTREG (NUM_BANKS == 1)
+        .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS)
    ) core_rsp_req (
        .clk       (clk),
        .reset     (reset),