simulation framework refactoring
This commit is contained in:
Blaise Tine
@@ -1,90 +1,38 @@
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CFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors
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#CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
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RTLSIM_DIR = ../../sim/rtlsim
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CFLAGS += -DUSE_RTLSIM -fPIC -Wno-maybe-uninitialized
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CFLAGS += -I../../include -I../../../hw/simulate -I../../../hw
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CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors
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#CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors
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# control RTL debug print states
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DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
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DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
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DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG
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DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA
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DBG_PRINT_FLAGS += -DDBG_PRINT_MEM
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DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
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DBG_PRINT_FLAGS += -DDBG_PRINT_AVS
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DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
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CXXFLAGS += -I../include -I../../hw -I$(RTLSIM_DIR) -I$(RTLSIM_DIR)/../common
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DBG_FLAGS += $(DBG_PRINT_FLAGS)
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DBG_FLAGS += -DDBG_CACHE_REQ_INFO
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LDFLAGS += $(RTLSIM_DIR)/librtlsim.a
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CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1
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# Position independent code
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CXXFLAGS += -fPIC
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CFLAGS += $(CONFIGS)
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CFLAGS += -DDUMP_PERF_STATS
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# Add external configuration
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CXXFLAGS += $(CONFIGS)
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LDFLAGS += -shared -pthread
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#LDFLAGS += -dynamiclib -pthread
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# Dump perf stats
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CXXFLAGS += -DDUMP_PERF_STATS
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ifdef AXI_BUS
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TOP = Vortex_axi
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CFLAGS += -DAXI_BUS
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else
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TOP = Vortex
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endif
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LDFLAGS += -shared
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RTL_DIR = ../../hw/rtl
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DPI_DIR = ../../hw/dpi
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SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
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SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp
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FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src
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RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE)
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VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic
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VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO
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VL_FLAGS += --x-initial unique --x-assign unique
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VL_FLAGS += verilator.vlt
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VL_FLAGS += $(CONFIGS)
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# Enable Verilator multithreaded simulation
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#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
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#VL_FLAGS += --threads $(THREADS)
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# Debugigng
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ifdef DEBUG
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VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS)
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CFLAGS += -DVCD_OUTPUT $(DBG_FLAGS)
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else
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VL_FLAGS += -DNDEBUG
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CFLAGS += -DNDEBUG
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endif
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SRCS = vortex.cpp ../common/vx_utils.cpp
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# Enable perf counters
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ifdef PERF
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VL_FLAGS += -DPERF_ENABLE
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CFLAGS += -DPERF_ENABLE
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CXXFLAGS += -DPERF_ENABLE
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endif
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# ALU backend
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VL_FLAGS += -DIMUL_DPI
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VL_FLAGS += -DIDIV_DPI
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# FPU backend
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FPU_CORE ?= FPU_DPI
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VL_FLAGS += -D$(FPU_CORE)
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PROJECT = libvortex.so
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# PROJECT = libvortex.dylib
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all: $(PROJECT)
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$(PROJECT): $(SRCS)
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verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
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make -j -C obj_dir -f V$(TOP).mk
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$(MAKE) -C $(RTLSIM_DIR) static
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$(CXX) $(CXXFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT)
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clean:
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rm -rf $(PROJECT) obj_dir
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$(MAKE) -C $(RTLSIM_DIR) clean-objdir
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rm -rf $(PROJECT) *.o .depend
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@@ -1,64 +0,0 @@
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#pragma once
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#include <stdio.h>
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#include <stdint.h>
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class RAM {
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private:
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mutable uint8_t *mem_[(1 << 12)];
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uint8_t *get(uint32_t address) const {
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uint32_t block_addr = address >> 20;
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uint32_t block_offset = address & 0x000FFFFF;
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if (mem_[block_addr] == NULL) {
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mem_[block_addr] = new uint8_t[(1 << 20)];
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}
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return mem_[block_addr] + block_offset;
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}
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public:
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RAM() {
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for (uint32_t i = 0; i < (1 << 12); i++) {
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mem_[i] = NULL;
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}
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}
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~RAM() {
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this->clear();
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}
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size_t size() const {
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return (1ull << 32);
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}
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void clear() {
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for (uint32_t i = 0; i < (1 << 12); i++) {
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if (mem_[i]) {
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delete [] mem_[i];
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mem_[i] = NULL;
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}
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}
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}
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void read(uint32_t address, uint32_t length, uint8_t *data) const {
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for (unsigned i = 0; i < length; i++) {
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data[i] = *this->get(address + i);
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}
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}
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void write(uint32_t address, uint32_t length, const uint8_t *data) {
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for (unsigned i = 0; i < length; i++) {
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*this->get(address + i) = data[i];
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}
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}
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uint8_t& operator[](uint32_t address) {
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return *get(address);
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}
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const uint8_t& operator[](uint32_t address) const {
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return *get(address);
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}
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};
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@@ -1,10 +0,0 @@
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`verilator_config
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lint_off -rule BLKANDNBLK -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule UNOPTFLAT -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule WIDTH -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*"
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lint_off -file "../rtl/fp_cores/fpnew/*"
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@@ -8,15 +8,11 @@
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#include <vortex.h>
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#include <VX_config.h>
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#include <ram.h>
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#include <mem.h>
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#include <util.h>
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#include <simulator.h>
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///////////////////////////////////////////////////////////////////////////////
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inline size_t align_size(size_t size, size_t alignment) {
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assert(0 == (alignment & (alignment - 1)));
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return (size + alignment - 1) & ~(alignment - 1);
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}
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using namespace vortex;
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///////////////////////////////////////////////////////////////////////////////
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@@ -58,7 +54,7 @@ private:
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class vx_device {
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public:
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vx_device() {
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vx_device() : ram_((1<<12), (1<<20)) {
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mem_allocation_ = ALLOC_BASE_ADDR;
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}
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@@ -92,7 +88,7 @@ public:
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}
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printf("\n");*/
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ram_.write(dest_addr, asize, (const uint8_t*)src + src_offset);
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ram_.write((const uint8_t*)src + src_offset, dest_addr, asize);
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return 0;
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}
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@@ -101,7 +97,7 @@ public:
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if (src_addr + asize > ram_.size())
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return -1;
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ram_.read(src_addr, asize, (uint8_t*)dest + dest_offset);
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ram_.read((uint8_t*)dest + dest_offset, src_addr, asize);
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/*printf("VXDRV: download %ld bytes to 0x%lx:", size, uintptr_t((uint8_t*)dest + dest_offset));
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for (int i = 0; i < (asize / CACHE_BLOCK_SIZE); ++i) {
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